- 您現在的位置：買賣IC網 > PDF目錄363893 > W6612 (WINBOND ELECTRONICS CORP) Dual PCM Codec(雙通道PCM編解碼器) PDF資料下載
參數資料
| 型號： | W6612 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Dual PCM Codec(雙通道PCM編解碼器) |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 9/21頁 |
| 文件大小： | 161K |
| 代理商： | W6612 |
W6612
Publication Release Date: October 1998
- 9 -
Revision A1
The received PCM will be processed by two paths depended by the mode selection, see Table 6-1.
One path converts the 8-bit Log-PCM into 14 bit linear PCM via A/Mu Law expander. The other one is
sent 14 bit linear PCM directly. The finial 14-bit linear is sent into
Σ
codec filter to convert into the
analog signal.
6.3.3. Frame Sync. Types
The frame sync operation uses three industrial control types for the transfer of the PCM data words.
These three types are the long frame sync , short frame sync and GCI frame sync.
6.3.3.1. Long Frame Sync
The long frame sync types for various data rates are shown in Figure 6-1 and 6-2. The bit rate for the
PCM is determined by the mode selection MODE1, MODE0 pin, shown in Table 6-1. The length of
the frame sync is calculated by the number of falling edges at the BCLKT1, BCLKT2 or BCLKR1,
BCLKR2 pin when the frame sync FST1, FST2 or FSR1, FSR2 pin is high.When the frame sync is
held logic one for two consecutive falling edges of the BCLKT1/2(BCLKR1/2)
, the device is in
long frame sync mode. The device shifts out the data on the DT1 or DT2 pin at the BCLKT1 or
BCLKT2 rising edge and shifts in the data on the DR1 or DR2 pin at the BCLKR1 or BCLKR2 falling
edge. The PCM data remain low impedence until seven and a half data clock cycles for 64K bps
if
frame sync cycle is less than eight data clcok
and thirteen and a half data clock cycles for 112
Kbps
if frame sync cycles is less than fourteen data clcok
. After the data transmission, the
DT1(DT2) outputs will return to high impedence state. The length of the frame sync may be changed
on a frame by frame basis.
6.3.3.2. Short Frame Sync
The short frame sync types for 64 Kbps or 112 kbps PCM, controlled by the MODE1, MODE0 pin.
The timing is shown in Figure 6-3 and 6-4. The length of the frame sync is equal to 1. The device
shifts out data on the DT1 or DT2 pin at the BCLKT1 or BCLKT2 rising edge and shifts in data on the
DR1 or DR2 pin at the BCLKR1 or BCLKR2 falling edge. The DT1(DT2) pin is going low impedance
when the logic AND of the FST1(FST2) pin and BCLKT1(BCLKT2) pin is the rising edge in the first.
The PCM data remain low impedence until seven and a half data clock cycles for 64 Kbps and
thirteen and a half data clock cycles for 112 k bps. After the data transmission, the DT1(DT2) outputs
will return to high impedence state. Switching between long frame sync and short frame sync without
going through a power down operation is not recommended.
6.3.3.3. GCI(General Circuit Interface) Frame Sync
The GCI frame sync is for two B channels access interface in ISDN application. The type is selected
by
BCLKR1
pin when the BCLKR1 pin is held low. This interface is only suitable for 8-bit Log-PCM
data, not 14-bit linear PCM data. The timing is shown in Figure 6-5. The timing is controlled by 4 pins,
FSC(FST1), DCL(BCLKT1), Dout(DT1), and Din(DR1). The pulse length of the frame sync(FSC) is
equal to 1 clock of DCL(BCLKT1). The DCL(BCLKT1) clcok rate is twice the actual PCM data rate.
The PCM data for Dout(DT1) or Din(DR1) is two 8-bit B channel data, i.e., 16 DCL(BCLKT1) clcok
rate. The previous 8 bit data is for Codec1 , and the left 8 bit data is for Codec 2. The Dout pin is
going low impedance when the logic AND of the FSC pin and DCL pin is high and remains the low
impedance for 15 and 1/2 DCL cycles. Note if the codec 1 enters the power down, the control timing
is switched to the Codec 2, FSC(FST2), DCL(BCLKT2), Dout(DT2), and Din(DR2). Meanwhile, the
output of Codec 1 part becomes the high impedance. If the Codec 2 is power down, the output of
Codec 2 part becomes the high impedance.
相關PDF資料 |
PDF描述 |
|---|---|
| W6630CR | Stereo Audio DAC(立體聲D/A轉換器) |
| W6631CS | Stereo Audio DAC(立體聲音頻數模轉換器) |
| W6631 | STEREO AUDIO DAC |
| W6662CF | CCD(Correlated Double Sampler)/CIS(Contact Image Sensors) Analog Front End Signal Processor.(耦合采樣器／接觸圖象傳感器模擬前端信號處理器) |
| W66880CF | VFD(Vacuum Fluorescent Display) Controller/Driver(VFD驅動器/控制器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W66125ASX-1 | 制造商:Magnecraft 功能描述:Relay SSR 20mA 280V AC-IN 125A 660V AC-OUT 4-Pin |
| W66125DSX-1 | 制造商:Magnecraft 功能描述:Relay SSR 16mA 32V DC-IN 125A 660V AC-OUT 4-Pin |
| W6630CR | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEREO AUDIO DAC |
| W6631 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEREO AUDIO DAC |
| W6631CS | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEREO AUDIO DAC |
發布緊急采購，3分鐘左右您將得到回復。