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參數資料
| 型號： | W6612 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Dual PCM Codec(雙通道PCM編解碼器) |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 5/21頁 |
| 文件大小： | 161K |
| 代理商： | W6612 |
W6612
Publication Release Date: October 1998
- 5 -
Revision A1
4.2. Analog Interface, continued
PIN NAME
PO1+
PIN NO.
41
I/O
O
FUNCTION
This pin is the first non-inverting power amplifier output. This pin
can drive the a 300
load to 1.579 volt peak referenced to the
VAG pin.
This pin is the second non-inverting analog output of the receive
smoothing filter. This pin can typically drive a 2K
load to 1.579
volt peak referenced to the analog ground level.
This pin is the second inverting input to the PO1- power amplifier. It
is dc referenced to the VAG pin. This pin and PO1- are used to set
the gain by using external resistors.
This pin is the second inverting power amplifier output. This pin can
drive the a 300
load to 1.579 volt peak referenced to the VAG
pin.
This pin is the second non-inverting power amplifier output. This
pin can drive the a 300
load to 1.579 volt peak referenced to the
VAG pin.
RO2
11
O
PI2
12
I
PO2-
13
O
PO2+
14
O
4.3. PCM Serial Interface
PIN NAME
MCLK
PIN NO.
26
I/O
I
FUNCTION
This pin is the system master clock input pin. It is 2.048 MHz or
1.536 MHz. It must be
synchronized with FST1, FST2 pin.
This pin is an 8 KHz pulse for the first transmission of frame syncs.
It enables the DT1 PCM output by BCLKT1 pin.
This pin is the transmit bit clock. It shifts out the data on the DT1
pin on the rising edge. The frequency may vary from 128K to 4096
KHz.
This pin is tri-state PCM output data for transmission controlled by
FST1 and BCLKT1 pin.
No connection for reservation
This pin is an 8 KHz pulse to receive the first frame syncs. It
enables the DR1 PCM input by BCLKR1 pin.
This pin is the receive bit clock. It shifts data on the DR1 pin into
the chip on the falling edge. The frequency varies from 128K to
4096 KHz.
This pin is the PCM receive input data controlled by the FSR1 and
BCLKR1 pins.
This pin is an 8 KHz pulse for the first transmission of frame syncs.
It enables the DT1 PCM output by BCLKT1 pin.
FST1
32
I
BCLKT1
33
I
DT1
31
O
NC
FSR1
30
28
O
I
BCLKR1
29
I
DR1
27
I
FST2
24
I
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