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參數資料
| 型號： | W6612 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Dual PCM Codec(雙通道PCM編解碼器) |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 11/21頁 |
| 文件大小： | 161K |
| 代理商： | W6612 |
W6612
Publication Release Date: October 1998
- 11 -
Revision A1
BCLKT1/BCLKT2
(BCLKR1/BCLKR2)
FST1/FST2
(FSR1/FSR2)
DT1/DT2
1
2
3
4
12
13
14
D13
D12
D11
D10
MSB
LSB
D2
D1
D0
DR1/DR2
D13
D12
Don't Care
Don't Care
D11
D10
MSB
LSB
D2
D1
D0
Figure 6-4 Short Frame Sync for 112 Kbps PCM Timing
DCL(BCLKT1)
FSC(FST1)
Dout(DT1)
MSB
LSB
D7
Channel 1
Channel 2
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Din(DR1)
MSB
LSB
D7
Channel 1
Channel 2
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6-5 GCI Frame Sync for 128 Kbps PCM Timing
6.4. Sequence and Control
This block generates some internal clocks, providing clocks for
Σ
codec-filter operation. The master
clock MCLK pin, which supports the clock of the digital circuit, may be asynchronous to all other
blocks but synchronous to FST1 and FST2 frame sync pulse, 8 KHz. Its frequency is 2.048 MHz or
1.536 MHz. As for jitter tolerence of MCLK pin, it is
146.5 nS for 2.048 MHz; but 260 nS for 1.536
MHz
. In addition, the duty cycle of MCLK pin must be
50
%
The rising edge of MCLK pin must be approximately aligned with the rising edge of the FST1 or FST2
pin depent on whether the codec of device is power down. If the device does not enter the power
down mode,
the master clock is refered to FST1 in default
. If the codec1 is power down, the
master clock is refered to FST2 pin. The device will automatically detect the clock rate of MCLK pin
by a prescaler circuit for MCLK and FST1 (or FST2).
When the Codec is start-up initially such as power-on reset or power-up after power-down, the steady
codec output data will be delay by about 60 samples.
When the PDI1 pin is held to logic 0, the codec 1 will become the hardware power down. The VAG,
TG1, RO1, PO1, DT1 outputs enter high impedance. When the PDI2 pin is held to logic 0, the codec
2 will become the hardware power down. The TG2, RO2, PO2, DT2 outputs are all high impedance.
If the device is
GCI mode
, the channel can be powered down separatedly by PDI1 or PDI2 pin. The
device is built-in
power-on reset circuit in default
.
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