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參數資料
| 型號： | W48S87-72 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Desktop/Notebook Frequency Generator(桌上型電腦/筆記本電腦系統頻率發生器) |
| 中文描述： | 臺式機/筆記本頻率發生器（桌上型電腦/筆記本電腦系統頻率發生器） |
| 文件頁數： | 6/19頁 |
| 文件大小： | 202K |
| 代理商： | W48S87-72 |
W48S87-72
PRELIMINARY
6
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the
“
reserved
”
bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 4
gives the bit formats for registers located in Data
Bytes 0
–
7.
Table 5
details additional frequency selections that are avail-
able through the serial data interface.
Table 6
details the select functions for Byte 0, bits 1 and 0.
Table 4. Data Bytes 0
–
7 Serial Configuration Map
Bit(s)
Data Byte 0
7
6
5
4
3
2
1
–
0
Affected Pin
Pin No.
Control Function
Bit Control
Default
Pin Name
0
1
--
--
--
--
23
22
--
--
--
--
--
(Reserved)
(Reserved)
SEL_4
SEL_3
48-/24-MHz Clock Output Frequency Selection
48-/24-MHz Clock Output Frequency Selection
Bit 1
Bit 0
Function (See
Table 6
for function details)
0
0
Normal Operation
0
1
Test Mode
1
0
Spread Spectrum On
1
1
All Outputs Three-stated
--
Refer to
Table 5
Refer to
Table 5
Refer to
Table 5
24MHz
24MHz
--
0
0
0
0
0
0
00
48/24MHZ
48/24MHZ
--
48MHz
48MHz
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
23
22
--
--
38
39
41
42
48/24MHZ
48/24MHZ
--
--
CPU3
CPU2
CPU1
CPU0
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
--
--
Low
Low
Low
Low
Active
Active
--
--
Active
Active
Active
Active
1
1
0
0
1
1
1
1
--
8
16
14
13
12
11
9
--
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
0
1
1
1
1
1
1
1
PCI_F
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
26
27
29
30
32
33
35
36
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
1
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