
W48S87-72
PRELIMINARY
15
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8 MHz
Min.
Typ.
CPU = 60 MHz
Min.
Typ.
Unit
Max.
Max.
t
P
f
Period
Measured on rising edge at 1.5V
30
33.3
ns
Frequency, Actual
Determined by PLL divider ratio
33.4
29.938
MHz
t
H
t
L
t
R
t
F
t
D
High Time
Duration of clock cycle above 2.4V
12
13.3
ns
Low Time
Duration of clock cycle below 0.4V
12
13.3
ns
Output Rise Edge Rate
1
4
1
4
V/ns
Output Fall Edge Rate
1
4
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at
1.5V
45
51
55
45
51
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maxi-
mum difference of cycle time between
two adjacent cycles.
250
250
ps
t
SK
t
O
Output Skew
Measured on rising edge at 1.5V
250
250
ps
CPU to PCI Clock
Skew
Covers all CPU/PCI outputs. Measured
on rising edge at 1.5V. CPU leads PCI
output.
1
4
1
4
ns
f
ST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
30
30
I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Min.
Typ.
Unit
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
t
R
t
F
t
D
f
ST
Output Rise Edge Rate
1
4
V/ns
Output Fall Edge Rate
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at 1.25V
45
52.5
55
%
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
15