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參數(shù)資料
| 型號(hào)： | W48S87-72 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Desktop/Notebook Frequency Generator(桌上型電腦/筆記本電腦系統(tǒng)頻率發(fā)生器) |
| 中文描述： | 臺(tái)式機(jī)/筆記本頻率發(fā)生器（桌上型電腦/筆記本電腦系統(tǒng)頻率發(fā)生器） |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 202K |
| 代理商： | W48S87-72 |
W48S87-72
PRELIMINARY
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
O
Pin Description
CPU0:2
52, 51, 49
CPU Outputs 0 through 3:
These four CPU outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI0:5
9, 11, 12,
13, 14, 16
O
PCI Bus Outputs 0 through 5:
These six PCI outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
8
O
Free Running PCI Output:
Unlike PCI0:5 outputs, this output is not controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM0:5
36, 35, 33,
32, 30, 29
O
SDRAM Clock Outputs 0 through 5:
These six SDRAM clock outputs run
synchronous to the CPU clock outputs. Output voltage swing is controlled by
voltage applied to VDDQ3.
SDRAM Clock Output 6 or CPU Clock Output Stop Control:
This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM
clock output 6.
Regarding use as a CPU_STOP# input: When brought LOW, clock outputs
CPU0:3 are stopped LOW after completing a full clock cycle (2
–
3 CPU clock
latency). When brought HIGH, clock outputs CPU0:3 are started beginning with
a full clock cycle (2
–
3 CPU clock latency).
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM Clock Output 7 or PCI Clock Output Stop Control:
This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM
clock output 7.
PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW
after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5
are started beginning with a full clock cycle. Clock latency provides one PCI_F
rising edge of PCI clock following PCI_STOP# state change.
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
I/O APIC Clock Output:
Provides 14.318-MHz fixed frequency. The output
voltage swing is controlled by VDDQ2.
48-MHz / 24-MHz Output:
Fixed clock outputs that default to 48 MHz following
device power-up. Either or both can be changed to 24 MHz through use of the
serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled
by voltage applied to VDDQ3
SDRAM6/
CPU_STOP#
27
I/O
SDRAM7/
PCI_STOP#
26
I/O
IOAPIC
45
O
48/24MHz
22, 23
O
REF0:1
2, 1
O
Fixed 14.318-MHz Outputs 0 through 1:
Used for various system applica-
tions. Output voltage swing is controlled by voltage applied to VDDQ3. REF0
is stronger than REF1 and should be used for driving ISA slots.
CPU_2.5#
47
I
Set to logic 0 for V
DDQ2
= 2.5V (0 to 2.5V CPU output swing).
60- or 66-MHz Input Selection:
Selects power-up default CPU clock frequency
as shown in
Table 1
on page 1 (also determines SDRAM and PCI clock fre-
quency selections). Can be used to change CPU clock frequency while device
is in operation if serial data port bits 0
–
2 of Byte 7 are logic 1 (default power-
up condition).
Crystal Connection or External Reference Frequency Input:
This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
Crystal Connection:
An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
60/66_SEL
18
I
X1
4
I
X2
5
I
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