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參數資料
型號： W3H64M72E-667ES
英文描述： 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
中文描述： 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝
文件頁數： 27/30頁
文件大小： 956K
代理商： W3H64M72E-667ES
W3H64M72E-XSBX
27
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
AC TIMING PARAMETERS
(continued)
-55°C ≤ T
A
< +125°C; V
CCQ
= + 1.8V ± 0.1V, V
CC
= +1.8V ± 0.1V
Parameter
Symbol
533Mbs CL4
Min
0.6
500
250
500
375
2
55
10
15
50
40
7.5
15
t
WR
+ t
RP
7.5
15
t
RP
+ t
CK
2
t
IS
+t
IH
+ t
CK
127.5
400Mbs CL3
Min
0.6
600
350
600
475
2
55
10
15
50
40
7.5
15
t
WR
+ t
RP
10
15
t
RP
+ t
CK
2
t
IS
+t
IH
+ t
CK
127.5
Unit
Max
Max
C
Address and control input pulse width for each input
t
IPW
t
IS
a
t
IS
b
t
IH
a
t
IH
b
t
CCD
t
RC
t
RRD
t
RCD
t
FAW
t
RAS
t
RTP
t
WR
t
DAL
t
WTR
t
RP
t
RPA
t
MRD
t
DELAY
t
RFC
t
REFI
t
REFI
IT
t
XSNR
t
XSRD
t
lSXR
t
AOND
t
ACN
t
AOFD
t
AOF
t
CK
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
ns
ns
μs
μs
ns
t
CK
ps
t
CK
ps
t
CK
ps
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
REFRESH to Active or Refresh to Refresh command interval
Average periodic refresh interval (commercial)
Average periodic refresh interval (industrial)
Exit self refresh to non-READ command
Exit self refresh to READ
Exit self refresh timing reference
ODT tum-on delay
ODT turn-on
ODT turn-off delay
ODT tum-off
70,000
70,000
S
70,000
7.8
3.9
70,000
7.8
3.9
t
RPC(MIN)
+ 10
200
t
IS
2
t
AC(MIN)
2.5
t
AC(MIN)
t
AC(MIN)
+
2000
t
AC(MIN)
+
2000
3
8
12
2
6-AL
2
3
t
RFC(MIN)
+ 10
200
t
IS
2
t
AC(MIN)
2.5
t
AC(MIN)
t
AC(MIN)
+
2000
t
AC(MIN)
+
2000
3
8
12
2
6-AL
2
3
O
2
2
t
AC(MAX)
+ 1000
2.5
t
AC(MAX)
+ 600
2 x t
CK
+
t
AC(MAX)
+ 1000
2 x t
CK
+
t
AC(MAX)
+ 1000
t
AC(MAX)
+ 1000
2.5
t
AC(MAX)
+ 600
2 x t
CK
+
t
AC(MAX)
+ 1000
2 x t
CK
+
t
AC(MAX)
+ 1000
ODT tum-on (power-down mode)
t
AONPD
ps
ODT turn-off (power-down mode)
t
AOFPD
ps
ODT to power-down entry latency
ODT power-down exit latency
ODT enable from MRS command
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command
CKE minimum high/low time
t
ANPD
t
AXPD
t
MOD
t
XARD
t
XARDS
t
XP
t
CKE
t
CK
t
CK
ns
t
CK
t
CK
t
CK
t
CK
P
相關PDF資料
PDF描述
W3H64M72E-667ESC 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667ESI 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3HG128M64EEU665D4XXG 1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
W3HG128M64EEU806D4XXG 1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
W3HG128M64EEU-D4 1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
相關代理商/技術參數
參數描述
W3H64M72E-667ESC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667ESI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667ESM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667SB 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667SBC 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk
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