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參數(shù)資料
| 型號(hào)： | W3H64M72E-667ES |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁(yè)數(shù)： | 25/30頁(yè) |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-667ES |
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W3H64M72E-XSBX
25
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
AC TIMING PARAMETERS
-55°C ≤ T
A
< +125°C; V
CCQ
= + 1.8V ± 0.1V, V
CC
= +1.8V ± 0.1V
Parameter
Symbol
533Mbs CL4
400Mbs CL3
Unit
Min
3,750
5,000
0.48
0.48
Max
8,000
8,000
0.52
0.52
Min
5,000
5,000
0.48
0.48
Max
8,000
8,000
0.52
0.52
C
Clock cycle time
CL=4
CL=3
t
CK(4)
ps
ps
t
CK
t
CK
ps
t
CK(3)
CK high-level width
CK low-level width
Half clock period
t
CH
t
CL
t
HP
MIN (t
CH
, t
CL
)
MIN (t
CH
, t
CL
)
C
Absolute
t
CK
t
CK
abs
t
CK
AVG
(MIN)+
t
JIT
PER
(MIN)
t
CK
AVG
(MAX)+
t
JIT
PER
(MAX)
t
CK
AVG
(MIN)+
t
JIT
PER
(MIN)
t
CK
AVG
(MAX)+
t
JIT
PER
(MAX)
ps
Absolute CK high-level width
t
CH
abs
t
CK
AVG
(MIN)*
t
CH
AVG
(MIN)+
t
JIT
DTY
(MIN)
t
CK
AVG
(MAX)*
t
CH
AVG
(MAX)+
t
JIT
DTY
(MAX)
t
CK
AVG
(MIN)*
t
CH
AVG
(MIN)+
t
JIT
DTY
(MIN)
t
CK
AVG
(MAX)*
t
CH
AVG
(MAX)+
t
JIT
DTY
(MAX)
ps
Absolute CK low-level width
t
CL
abs
t
CK
AVG
(MIN)*
t
CL
AVG
(MIN)+
t
JIT
DTY
(MIN)
-125
-125
t
CK
AVG
(MAX)*
t
CL
AVG
(MAX)+
t
JIT
DTY
(MAX)
125
125
250
175
225
250
250
350
450
t
CK
AVG
(MIN)*
t
CL
AVG
(MIN)+
t
JIT
DTY
(MIN)
-125
-125
t
CK
AVG
(MAX)*
t
CL
AVG
(MAX)+
t
JIT
DTY
(MAX)
125
125
250
175
225
250
250
350
450
ps
C
Clock jitter - period
Clock jitter - half period
Clock jitter - cycle to cycle
Cumulative jitter error, 2 cycles
Cumulative jitter error, 3 cycles
Cumulative jitter error, 4 cycles
Cumulative jitter error, 5 cycles
Cumulative jitter error, 6-10 cycles
Cumulative jitter error, 11-50 cycles
t
JIT
PER
ps
ps
ps
ps
ps
ps
ps
ps
ps
t
JIT
DUTY
t
JIT
CC
t
ERR
2per
-175
-225
-250
-250
-350
-450
-175
-225
-250
-250
-350
-450
t
ERR
3per
t
ERR
4per
t
ERR
5per
t
ERR
6-10per
t
ERR
11-50per
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-667ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
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