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參數資料
| 型號： | W29N102C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K×16bit CMOS 3.3V Flash Memory(64K×16位以3.3V電源供電的CMOS閃速存儲器) |
| 中文描述： | 64K的× 16位的CMOS 3.3V的快閃記憶體（64K的× 16位以3.3V的電源供電的閃速存儲器的CMOS） |
| 文件頁數： | 4/21頁 |
| 文件大小： | 253K |
| 代理商： | W29N102C |
Preliminary W29N102C
- 4 -
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.
Program Operation
The W29N102C is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will interally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50
μ
S max. -
T
BP
) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W29N102C is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation is inhibited when V
DD
is less than
1.8V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-
out 10 mS before any write (erase/program) operation.
Data Polling (DQ
7 &
DQ
15
)- Write Status Detection
The W29N102C includes a data polling feature to indicate the end of a program or erase cycle.
When the W29N102C is in the internal program or erase cycle, any attempt to read DQ
7
or DQ
15
of
the last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
7
or DQ
15
will show the true data. Note that DQ
7
or DQ
15
will show logical "0" during
the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ
6
& DQ
14
)- Write Status Detection
In addition to data polling, the W29N102C provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
or
DQ
14
will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling
between 0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address
0001H outputs the device code (00BFh). The product ID operation can be terminated by a three-word
command sequence or an altenate one-word command sequence (see Command Definition table).
In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.
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