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參數資料
型號: WB1330
廠商: Cypress Semiconductor Corp.
英文描述: Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers(帶2.5-GHz和600-MHz預標定器的雙路串聯輸入PLL)
中文描述: 雙串行輸入鎖相環2.5千兆赫和600兆赫分頻器(帶2.5 - GHz的和600 - MHz的預標定器的雙路串聯輸入鎖相環)
文件頁數: 9/10頁
文件大小: 160K
代理商: WB1330
WB1330
9
Document #: 38-00826-B
Table 4. 7-Bit Swallow Counter (A) Truth Table
[10]
Divide Ratio A
PLL1 (High Frequency)
A7
A6
A5
A4
A3
A2
A1
0
X
0
0
0
0
0
0
1
X
0
0
0
0
0
1
:::
:::
:::
:::
:::
:::
:::
:::
62
X
1
1
1
1
1
0
63
PLL2 (Low Frequency)
X
1
1
1
1
1
1
0
X
X
X
0
0
0
0
1
X
X
X
0
0
0
1
:::
:::
:::
:::
:::
:::
:::
:::
14
X
X
X
1
1
1
0
15
X
X
X
1
1
1
1
Table 5. 11-Bit Programmable Counter (B) Truth Table
[11]
Divide Ratio B
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
2046
1
1
1
1
1
1
1
1
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table
[11]
Divide Ratio R
R15
0
R14
0
R13
0
R12
0
R11
0
R10
0
R9
0
R8
0
R7
0
R6
0
R5
0
R4
0
R3
0
R2
1
R1
1
3
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
:::
32766
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information
[12]
Ordering Code
WB1330
Package
Name
X
Package Type
20-pin TSSOP (0.173
wide)
TR
Tape and Reel Option
Notes:
10. B is greater than or equal to A.
11. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
12. Operating temperature range:
40
°
C to +85
°
C.
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter (0 to 63) and the 4-bit swallow counter (0 to 15).
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler.
The divide ratio N = (P * B) + A.
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).
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