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參數資料
| 型號： | WB1330 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers(帶2.5-GHz和600-MHz預標定器的雙路串聯輸入PLL) |
| 中文描述： | 雙串行輸入鎖相環2.5千兆赫和600兆赫分頻器（帶2.5 - GHz的和600 - MHz的預標定器的雙路串聯輸入鎖相環） |
| 文件頁數： | 7/10頁 |
| 文件大小： | 160K |
| 代理商： | WB1330 |
WB1330
7
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data into the locations given in
Table 1
.
Notes:
4.
5.
6.
7.
t1
–
t5 = 50 μs > t > 0.5 μs.
CLOCK may remain HIGH after latching in data.
DATA is shifted in with the MSB first.
For DATA definitions, refer to
Table 2
.
Serial Data Input Timing Waveform
[4, 5, 6, 7]
Timing Waveforms
(continued)
CLOCK
//
t2
LE
//
//
//
//
//
//
//
t1
t3
t4
t5
DATA
PD = MSB
PRE
B1
A7
CNT2
CNT1 = LSB
Table 1. Control Configuration
CNT1
CNT2
Function
0
0
Program Reference 2
: R = 3 to 32767, set PLL2 (low frequency) phase detector
polarity, set current in PLL2, set PLL2 three-state, set monitor selector to PLL2.
0
1
Program Reference 1:
R = 3 to 32767, set PLL1 (high frequency) phase detector
polarity, set current in PLL1, set PLL1 three-state, set monitor selector to PLL1
1
0
Program Counter for PLL2:
A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set power-
down to PLL2.
Program Counter for PLL1:
A = 0 to 63, B = 3 to 2047, set PLL1 prescaler ratio, set power-
down to PLL1.
1
1
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