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W712 USB Device Controller
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Oki Semiconductor
FUNCTIONAL DESCRIPTION
The W712 controller consists of two submodules, the Z712a hard macro, and the W712b soft macro, each
containing multiple function blocks. The Z712a includes the Protocol Engine, DPLL, and Timer Blocks.
The W712b includes the Status/Control, FIFO Control, Application Interface, Frame Timer Synthesizer,
and remote wakeup blocks.
Protocol Engine
The Protocol Engine handles the USB communication protocol. It performs packet sequencing, signal
generation/detection, CRC generation/checking, NRZI data encoding, bit-stuffing and packet ID (PID)
generation/decoding.
DPLL
The Digital Phase Locked Loop extracts the clock and data from the USB differential received data.
Timer
The Timer block monitors idle time on the USB bus.
Status/Control
The Status/Control block uses transfer type and FIFO state information to manage the reception and
transmission of USB data. It monitors the transaction status and communicates control events to the appli-
cation via the Application Interface.
FIFO Control
The FIFO control block manages all FIFO operations for transmitting and receiving USB data sets. The
W712 supports eight FIFOs (four transmit and four receive). They can be configured as described in the
table below.
Endpoints 3 and 7 are 2-level FIFOs which support up to two separate data sets of variable sizes. All FIFOs
have flags that detect a full or empty FIFO and have the capability of re-transmitting or re-receiving the
current data set.
FIFO Configuration
FIFO Type
Endpoint Address
Programmable
Function
Transmit
0
64 bytes
Control Transfers
Transmit
5
64 bytes
Interrupt and Bulk Transfers
Transmit
6
64 bytes
Interrupt and Bulk Transfers
Transmit
7
2 Kbytes
Isochronous, Interrupt, and Bulk Transfers
Receive
0
64 bytes
Control Transfers
Receive
1
64 bytes
Bulk Transfers
Receive
2
64 bytes
Bulk Transfers
Receive
3
2 Kbytes
Isochronous and Bulk Transfers