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參數資料
| 型號： | W712 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Universal Serial Bus (USB) Device Controller(通用串行總線控制器) |
| 中文描述： | 通用串行總線（USB）設備控制器（通用串行總線控制器） |
| 文件頁數： | 7/17頁 |
| 文件大小： | 205K |
| 代理商： | W712 |
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I
W712 USB Device Controller
I
5
Oki Semiconductor
Application Interface
Signal
Type
Assertion
Description
sys_clock
Input
—
Clock
low-speed operation.
. Attach a 12-MHz clock signal to this input for full-speed operation and 1.5 MHz for
sys_reset
Input
HIGH
W712 Reset.
cation module is required to assert this signal at power-on.
Asserting this signal HIGH resets the W712 mega macrofunction. The appli-
mwr_rdb
Input
—
Write/Read Select.
tion is in WRITE mode. When asserted LOW, the application is in READ mode. External
application logic asserts this signal HIGH when writing data to the transmit FIFOs or to the
register files. External application logic asserts this signal LOW when reading data from
the receiving FIFOs or from the register files. The register files contain information describ-
ing the function and transaction status.
When external application logic asserts this signal HIGH, the applica-
usb_reset
Output
HIGH
USB Reset
. This is the reset signal from the USB device controller.
[7:0]ma
Input
—
Address Bus.
controller.
These eight inputs receive the address of the register files in the USB device
[7:0]md
Input
—
Input Data Bus.
transmit FIFOs.
These eight inputs receive the data to be stored in the register files or
mrdyb
Input
LOW
Data Strobe.
lines are valid for writing. When asserted LOW and in READ mode, the data on the [7:0]pd
signals are valid for reading.
When asserted LOW and in WRITE mode, the data on the [7:0]md signal
[7:0]pd
Output
—
Output Data Bus
or the receive FIFOs.
. These eight outputs transmit data received from either the register files
[3:0]pkt_rdy
Output
HIGH
Packet Ready
FIFOs contains valid data. The application reads the data through the [7:0]pd bus.
. When the W712 asserts this signal, it indicates that one of the four receive
full_spden
Input
—
USB Full Speed Enable.
operation and “0” to select low-speed operation.
The application module sets this pin to “1” to select full-speed
setup_rdy
Output
HIGH
Setup Ready.
ceived from the USB bus.
Asserting this signal HIGH indicates an 8-byte SETUP data has been re-
iso_err
Output
HIGH
Isochronous Error.
ceived with DATA1 PID.
Used for loopback testing or to indicate isochronous data has been re-
validsof
Output
HIGH
Valid SOF
cates a valid SOF token is received when asserted HIGH.
. This signal is asserted for two bit times, asynchronous to sys_clock, and indi-
sel_ext_pll
Input
HIGH
Select External PLL
. Asserting this signal HIGH selects the external PLL option.
setup_rdy2
Output
HIGH
Second Setup Ready
been received, while internally the device controller still sees the “setup_rdy” signal assert-
ed. This signal will be asserted for two bit times, asynchronous to sys_clock.
. Asserting this signal HIGH indicates a new 8-byte SETUP DATA has
testmode
Input
HIGH
Testmode
. Asserting this signal invokes a loopback test mode.
validin
Output
HIGH
Valid IN
token is received when asserted HIGH.
. Asserted for two bit times, asynchronous to sys_clock, and indicates a valid IN
validout
Output
HIGH
Valid OUT
OUT token is received when asserted HIGH.
. Asserted for two bit times, asynchronous to sys_clock, and indicates a valid
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