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參數(shù)資料
| 型號： | W712 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Universal Serial Bus (USB) Device Controller(通用串行總線控制器) |
| 中文描述： | 通用串行總線（USB）設(shè)備控制器（通用串行總線控制器） |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 205K |
| 代理商： | W712 |
I
W712 USB Device Controller
I
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6
Oki Semiconductor
FIFO Interface
Signal
Type
Assertion
Description
[7:0]trx_out_data
Input
—
Transmit FIFO(s} data output
ing.
. Output data from the transmission RAM selected for read-
[7:0]rcv_out_data
Input
—
Receive FIFO(s) data output
. Output data from the receiving RAM selected for reading.
[7:0]trx_in_data
Output
—
Transmit FIFO(s) data input
. Input data to all transmission RAMs.
[2:0]trx_sel
Output
HIGH
Transmit FIFO(s) select
. Selects one of the seven transmission RAMs for reading.
[8:0]trx_wr_ptr
Output
—
Transmit FIFO(s) write pointer
. Write address to all transmission RAMs.
[8:0]trx_rd_ptr
Output
—
Transmit FIFO(s) read pointer
. Read address to all transmission RAMs.
[6:0]trx_wrb
Output
LOW
Transmit FIFO(s) write strobe
. Write enable. One bit per transmission RAM.
[7:0]rcv_in_data
Output
—
Receive FIFO(s) data input
. Input data to all receiving RAMs.
[2:0]rcv_sel
Output
HIGH
Receive FIFO(s) select
. Selects one of the seven receiving RAMs for reading.
[8:0]rcv_wr_ptr
Output
—
Receive FIFO(s) write pointer
. Write address to all receiving RAMs.
[8:0]rcv_rd_ptr
Output
—
Receive FIFO(s) read pointer
. Read address to all receiving RAMs.
[6:0]rcv_wrb
Output
LOW
Receive FIFO(s) write strobe
. Write enable. One bit per receiving RAM.
DPLL Interface
Signal
Type
Assertion
Description
osc_clk
Input
–
Oscillator Clock
signal for low-speed operation.
. Attach a 48 MHz clock signal for full-speed operation or a 6 MHz clock
usb_clk_ext
Input
–
USB Clock External
should run at 12 MHz for full-speed operation or 1.5 MHz for low-speed operation. If an
external DPLL is not used, this pin should be connected to VDD or GND.
. This is the output clock signal from an external DPLL. This clock
usb_rxd_out
Output
–
Synchronized USB Differential Received Data
tial receiver and is synchronized with the oscillator input. This signal connects to the ex-
ternal DPLL if it is used.
. This signal comes from the USB differen-
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