
Preliminary W6691
Publication Release Date: Sep 2001
5 Revision 1.1
9.5 AC Timing Test Conditions............................................................................................................. 104
10. ORDERING INFORMATION........................................................................................................104
11. PACKAGE DIMENSIONS ............................................................................................................105
LIST OF FIGURES
FIG.3.1 W6691 PIN CONFIGURATION - INTEL BUS MODE .............................................................10
FIG.3.2 W6691 PIN CONFIGURATION – MOTOROLA BUS MODE..................................................12
FIG.5.1 ISDN INTERNET PASSIVE S-CARD WITH TWO POTS CONNECTIONS ...........................16
FIG.5.2 ISDN PAXB APPLICATION.....................................................................................................17
FIG.6.1 W6691 FUNCTIONAL BLOCK DIAGRAM..............................................................................18
FIG.7.1 FRAME STRUCTURE AT S/T INTERFACE ...........................................................................21
FIG.7.2 W6691 WIRING CONFIGURATION IN TE APPLICATIONS..................................................22
FIG.7.3 EXTERNAL TRANSMITTER CIRCUITRY ..............................................................................23
FIG.7.4 EXTERNAL RECEIVER CIRCUITRY......................................................................................24
FIG.7.5 LAYER 1 ACTIVATION/DEACTION STATE DIAGRAM – NORMAL MODE..........................30
FIG.7.6 LAYER 1 ACTIVATION/DEACTIVATION STATE DIAGRAM - SPECIAL MODE...................31
FIG.7.7 LAYER 1 ACTIVATION/DEACTIVATION STATE DIAGRAM IN LT-S....................................34
FIG.7.9 SSP AND SCP TEST SIGNALS..............................................................................................41
FIG.7.10 GCI TE MODE CHANNEL STRUCTURE..............................................................................48
FIG.7.11 GCI NON –TERMINAL MODE CHANNEL STRUCTURE.....................................................49
LIST OF TABLES
TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE........................................................25
TABLE 7.2 LAYER 1 COMMAND CODES...........................................................................................28
TABLE 7.3 LAYER 1 INDICATION CODES.........................................................................................28
TABLE 7.4 LAYER 1 COMMAND CODES...........................................................................................33
TABLE 7.5 LAYER 1 INDICATION CODES.........................................................................................33
TABLE 7.8 D PRIORITY CLASSES .....................................................................................................35
TABLE 7.9 D PRIORITY COMMANDS/INDICATIONS........................................................................35
TABLE 7.10 MULTIFRAME STRUCTURE IN S/T INTERFACE..........................................................39
TABLE 8.1 D CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP....................................53
TABLE 8.2 GCI BUS CONTROL REGISTER ADDRESS MAP ...........................................................54
TABLE 8.3 MISCELLANEOUS REGISTER ADDRESS MAP ..............................................................55
TABLE 8.4 D CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP.....................................55