
Preliminary W6691
Publication Release Date: Sep 2001
3 Revision 1.1
8.5 GCI Bus Register Memory Map........................................................................................................ 57
8.6 Miscellaneous Register Memory Map .............................................................................................. 58
Table 8.6 Miscellaneous Register Memory Map .................................................................................... 58
8.7 D channel HDLC Controller Register Description............................................................................. 58
8.7.1 D_ch receive FIFO
8.7.2 D_ch transmit FIFO
8.7.3 D_ch command register
8.7.4 D_ch Mode Register
D_MODE Read/Write Address 03H..........................................................60
8.7.5 Interrupt Status Register
8.7.6 Interrupt Mask Register
8.7.7 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 06H .......................................63
8.7.8 D_ch Extended Interrupt Mask Register
8.7.9 D_ch Transmitter Status Register
8.7.10 D_ch Receive Status Register
8.7.11 D_ch SAPI Address Mask
D_SAM Read/Write Address 0EH ................................................66
8.7.12 D_ch SAPI1 Register
8.7.13 D_ch SAPI2 Register
8.7.14 D_ch TEI Address Mask
8.7.15 D_ch TEI1 Register
8.7.16 D_ch TEI2 Register
8.7.17 D_ch Receive Frame Byte Count High
8.7.18 D_ch Receive Frame Byte Count Low
8.8 GCI Bus Register Description........................................................................................................... 70
8.8.1 Channel Selection Register
CSEL Read/Write Address 18H................................................70
8.8.2 Command/Indication Receive Register
8.8.3 Command/Indication Transmit Register
8.8.4 S/Q Channel Receive Register
8.8.5 S/Q Channel Transmit Register
8.8.6 Monitor Receive Channel 0
8.8.7 Monitor Transmit Channel 0
8.8.8 Monitor Channel 0 Interrupt Register
8.8.9 Monitor Channel 0 Control Register
8.8.10 GCI Mode Control/Status Register
8.8.11 Monitor Receive Channel 1 Register
8.8.12 Monitor Transmit Channel 1 Register
8.8.13 Monitor Channel 1 Interrupt Register
8.8.14 Monitor Channel 1 Control Register
8.8.14 GCI CI1 Indication Register
D_RFIFO Read Address 00H......................................................................58
D_XFIFO Write Address 01H.....................................................................59
D_CMDR Write Address 02H .............................................................59
ISTA Read_clear Address 04H.......................................................61
IMASK Read/Write Address 05H...........................................................63
D_EXIM Read/Write Address 07
H
...............................64
D_XSTA Read Address 0AH..............................................65
D_RSTA Read Address 0BH ................................................65
D_SAP1 Read/Write Address 0FH........................................................67
D_SAP2 Read/Write Address 10H........................................................67
D_TAM Read/Write Address 11H ....................................................67
D_TEI1 Read/Write Address 12H..........................................................68
D_TEI2 Read/Write Address 13H..........................................................68
D_RBCH Read Address 16H.....................................69
D_RBCL Read Address 17H....................................69
CIR Read Address 1AH...............................................70
CIX Read/Write Address 1BH...................................71
SQR Read Address 1CH...........................................................71
SQX Read/Write Address 1DH...............................................72
MO0R Read Address 20H..........................................................72
MO0X Read/Write Address 21H................................................72
MO0I Read_clear Address 22H .................................73
MO0C Read/Write Address 23H.....................................73
GCR Read Address 26H.....................................74
MO1R Read Address 27H...........................................75
MO1X Read/Write Address 28H.......................75
MO1I Read_clear Address 29H ...............................76
MO1C Read/Write Address 2AH ....................................76
CI1R Read Address 31H........................................................77