
Preliminary W6691
Publication Release Date: Sep 2001
2 Revision 1.1
TABLE OF CONTENTS
REVISION HISTORY..............................................................................................................................7
1. GENERAL DESCRIPTION.................................................................................................................8
2. FEATURES.........................................................................................................................................9
3. PIN CONFIGURATIONS..................................................................................................................10
4. PIN DESCRIPTION ..........................................................................................................................13
5. SYSTEM DIAGRAM AND APPLICATIONS.....................................................................................16
6. BLOCK DIAGRAM...........................................................................................................................18
7. FUNCTIONAL DESCRIPTIONS.......................................................................................................19
7.1.1 Main Block Functions ......................................................................................................................19
7.1.2 Interface and Operating Modes.......................................................................................................20
7.2.1 S/T Interface Transmitter/Receiver..................................................................................................20
7.2.2 Receiver Clock Recovery And Timing Generation ..........................................................................25
7.2.3 Layer 1 Activation/Deactivation.......................................................................................................26
7.2.4 Layer 1 Activation /Deactivation in LT-S Mode................................................................................32
7.2.5 D Channel Access Control ..............................................................................................................35
7.2.6 Frame Alignment .............................................................................................................................36
7.2.7Multiframe Synchronization ..............................................................................................................38
7.2.8Test Functions..................................................................................................................................40
7.3 B Channel Switching ........................................................................................................................ 41
7.4 PCM Port.......................................................................................................................................... 42
7.5 D Channel HDLC Controller ............................................................................................................. 42
7.5.1 D Channel Message Transfer Modes..............................................................................................44
7.5.2 Reception of Frames in D Channel .................................................................................................45
7.5.3 Transmission of Frames in D Channel ............................................................................................46
7.6 GCI Mode Serial Interface Bus......................................................................................................... 47
7.6.1 GCI Mode C/I Channel Handling.....................................................................................................49
7.6.2 GCI Mode Monitor Channel Handling..............................................................................................50
7.7 8-bit Microprocessor Interface........................................................................................................ 52
8 REGISTER DESRCRIPTIONS..........................................................................................................53
8.1 D Channel HDLC Controller Register Address Map......................................................................... 53
8.2 GCI Bus Control Register Address Map........................................................................................... 54
8.3 Miscellaneous Register Address Map.............................................................................................. 55
8.4 D Channel HDLC Controller Register Memory Map......................................................................... 55