
The Western Design Center, Inc.
W65C816S Data Sheet
The Western Design Center
W65C816S
6
Table of Tables
Table 2-1 W65C816S Microprocessor Programming Model......................................................................12
Table 3-1 Pin Function Table.........................................................................................................................16
Table 4-1 Addressing Mode Summary..........................................................................................................27
Table 5-1 Absolute Maximum Ratings..........................................................................................................28
Table 5-2 DC Characteristics .........................................................................................................................29
Table 5-3 IDD vs. VDD...................................................................................................................................29
Table 5- 4 F Max vs. VDD...............................................................................................................................29
Table 5-4 W65C816S AC Characteristics.....................................................................................................30
Table 6-1 W65C816S Instruction Set-Alphabetical Sequence ....................................................................32
Table 6-2 Emulation Mode Vector Locations (8-bit Mode).........................................................................34
Table 6-3 Native Mode Vector Locations (16-bit Mode).............................................................................34
Table 6-4 OpCode Matrix...............................................................................................................................35
Table 6-5 Operation, Operation Codes, and Status Register (continued on following 4 pages)...............36
Table 6-6 Addressing Mode Symbol Table...................................................................................................41
Table 6-7 Instruction Operation (continued on following 6 pages)............................................................42
Table 6-8
Abbreviations..................................................................................................................................50
Table 7-1 Alternate Mnemonics.....................................................................................................................53
Table 7-2
Address Mode Formats..................................................................................................................54
Table 7-3 Byte Selection Operator.................................................................................................................55
Table 8-1 Caveats ............................................................................................................................................56
Table of Figures
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram..................................................11
Figure 3-1
W65C816S 44 Pin PLCC Pinout .................................................................................................13
Figure 3-2
W65C816S 40 Pin PDIP Pinout...................................................................................................14
Figure 3-3
W65C816S 44 PIN QFP Pinout ...................................................................................................15
Figure 5-1 General Timing Diagram.............................................................................................................31
Figure 6-1
Bank Address Latching Circuit....................................................................................................51