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參數(shù)資料
| 型號(hào)： | W65C816S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 16/62頁 |
| 文件大?。?/td> | 1129K |
| 代理商： | W65C816S |
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The Western Design Center, Inc.
W65C816S Data Sheet
The Western Design Center
W65C816S
16
Table 3-1 Pin Function Table
Pin
Description
A0-A15
ABORTB
BE
PHI2
D0-D7
E
IRQB
MLB
MX
NC
NMIB
RDY
RESB
RWB
VDA
VPB
VPA
VDD
VSS
Address Bus
Abort Input
Bus Enable
Phase 2 In Clock
Data Bus/Bank Address Bus
Emulation OR Native Mode Select
Interrupt Request
Memory Lock
Memory and Index Register Mode Select
No Connect
Non-Maskable Interrupt
Ready
Reset
Read/Write
Valid Data Address
Vector Pull
Valid Program Address
Positive Power Supply
Internal Logic Ground
3.1 Abort (ABORTB)
The Abort (ABORTB) negative pulse active input is used to abort instructions (usually due to an Address Bus
condition). A negative transition will inhibit modification of any internal register during the current instruction.
Upon completion of this instruction, an interrupt sequence is initiated. The location of the aborted OpCode is
stored as the return address in stack memory. The Abort vector address is 00FFF8,9 (Emulation mode) or
00FFE8,9 (Native mode). Note that ABORTB is a pulse-sensitive signal; i.e., an abort will occur whenever there
is a negative pulse (or level) on the ABORTB pin during a PHI2 clock.
3.2 Address Bus (A0-A15)
The sixteen Address Bus (A0-A15) output lines along with the bank address (multiplexed on the first half cycle of
the Data Bus (D0-D7) pins) form the 24-bit Address Bus for memory and I/O exchange on the Data Bus. When
using the W65C816S, the address lines may be set to the high impedance state by the Bus Enable (BE) signal.
3.3 Bus Enable (BE)
The Bus Enable (BE) input signal allows external control of the Address and Data Buffers, as well as the RWB
signal. With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are active
during the first half of every cycle and the second half of a write cycle. When BE is low, these buffers are
disabled. Bus Enable is an asynchronous signal.
3.4 Data/Bank Address Bus (D0-D7)
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| W65C816S6PG-14 | 功能描述:微處理器 - MPU 8/16-bit Microprocessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| W65C816S6PLG-14 | 功能描述:微處理器 - MPU 8/16-bit Microprocessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| W65C816S8P-14 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| W65C816S8PL-14 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| W65C816S8Q-14 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
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