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參數(shù)資料
| 型號： | W48S87-72H |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | 66.8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 248K |
| 代理商： | W48S87-72H |
W48S87-72
3
PWR_DWN#
44
I
Power-Down Control:
When this input is LOW, the device goes into a low-
power standby condition. All outputs are actively held LOW while in power-
down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing
a full clock cycle (2
–
4 CPU clock cycle latency). When brought HIGH, CPU,
SDRAM, and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
MODE
6
I
Mode Control:
This input selects the function of device pin 26
(SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to descrip-
tion for those pins.
Serial Data Input:
Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
SDATA
19
I/O
SCLOCK
20
I
Serial Clock Input:
Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
VDDQ3
7, 15, 21, 25
28, 34, 48
P
Power Connection:
Power supply for PCI0:5, REF0:1, and 48/24MHz output
buffers. Connected to 3.3V supply.
VDDQ2
46, 40
P
Power Connection:
Power supply for IOAPIC0, CPU0:3 output buffer. Con-
nected to 2.5V supply.
Ground Connection:
Connect all ground pins to the common system ground
plane.
GND
3, 10, 17,
24, 31, 37,
43
G
Pin Definitions
(continued)
Pin Name
Pin
No.
Pin
Type
Pin Description
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