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參數(shù)資料
| 型號： | W48S87-72H |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | 66.8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 248K |
| 代理商： | W48S87-72H |
W48S87-72
16
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Min.
Typ.
Unit
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
t
R
t
F
t
D
f
ST
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
50
55
%
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
16
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Min.
Typ.
Unit
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
t
R
t
F
t
D
f
ST
Output Rise Edge Rate
0.5
2
V/ns
Output Fall Edge Rate
0.5
2
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
40
48/24MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
f
Description
Test Condition/Comments
Determined by PLL divider ratio
(see n/m below)
CPU = 60/66.8 MHz
Unit
MHz
Min.
Typ.
Max.
Frequency, Actual
48.008/24.004
f
D
m/n
Deviation from 48 MHz
(48.008
–
48)/48
+167
ppm
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
t
R
t
F
t
D
f
ST
Output Rise Edge Rate
0.5
2
V/ns
Output Fall Edge Rate
0.5
2
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
50
55
%
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
40
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