- 您現在的位置：買賣IC網 > PDF目錄363886 > W3H32M72E-SBC 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package PDF資料下載
參數資料
| 型號： | W3H32M72E-SBC |
| 英文描述： | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 32M × 72配置DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 7/30頁 |
| 文件大小： | 934K |
| 代理商： | W3H32M72E-SBC |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
W3H32M72E-XSBX
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
low level must be applied to the ODT ball (all other
inputs may be undefined, I/Os and outputs must be
less than V
CCQ
during voltage ramp time to avoid
DDR2 SDRAM device latch-up). At least one of the
following two sets of conditions (A or B) must be
met to obtain a stable supply state (stable supply
defined as V
CC
, V
CCQ
, V
REF
, and V
TT
are between
their minimum and maximum values as stated in
Table20):
A. single power source) The V
CC
voltage ramp
from 300mV to V
CC
(MIN) must take no longer
than 200ms; during the V
CC
voltage ramp, |V
CC
-
V
CCQ
| ≤ 0.3V. Once supply voltage ramping
is complete (when V
CCQ
crosses V
CC
(MIN)),
Table20 specifications apply.
V
CC
, V
CCQ
are driven from a single power
converter output
V
TT
is limited to 0.95V MAX
V
REF
tracks V
CCQ/2
; V
REF
must be within
±0.3V with respect to V
CCQ/2
during supply
ramp time
V
CCQ
≥
V
REF
at all times
B. multiple power sources) V
CC
≥ V
CCQ
must be
maintained during supply voltage ramping, for
both AC and DC levels, until supply voltage
ramping completes (V
CCQ
crosses V
CC
[MIN]).
Once supply voltage ramping is complete,
Table20 specifications apply.
Apply V
CC
before or at the same time as
V
CCQ
; V
CC
voltage ramp time must be ≤
200ms from when V
CC
ramps from 300mV to
V
CC
(MIN)
Apply V
CCQ
before or at the same time as
V
TT
; the V
CCQ
voltage ramp time from when
V
CC
(MIN) is achieved to when V
CCQ
(MIN)
is achieved must be ≤ 500ms; while V
CC
is
ramping, current can be supplied from V
CC
through the device to V
CCQ
V
REF
must track V
CCQ/2,
V
REF
must be within
±0.3V with respect to V
CCQ/2
during supply
ramp time; V
CCQ
≥ V
REF
must be met at all
times
Apply V
TT
; The V
TT
voltage ramp time from
when V
CCQ
(MIN) is achieved to when V
TT
(MIN) is achieved must be no greater than
500ms
2. For a minimum of 200μs after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands
and take CKE HIGH.
3. Wait a minimum of 400ns, then issue a
PRECHARGE ALL command.
4. ssue an LOAD MODE command to the EMR(2).
(To issue an EMR(2) command, provide LOW to
BA0, provide HIGH to BA1.)
5. ssue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0
and BA1.)
6. ssue an LOAD MODE command to the EMR to
enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0, provide HIGH to BA0.
Bits E7, E8, and E9 can be set to “0” or “1”; Micron
recommends setting them to “0.”
7. ssue a LOAD MODE command for DLL RESET.
200 cycles of clock input is required to lock the
DLL. (To issue a DLL RESET, provide HIGH to A8
and provide LOW to BA1, and BA0.) CKE must be
HIGH the entire time.
8. ssue PRECHARGE ALL command.
9. ssue two or more REFRESH commands, followed
by a dummy WRITE.
相關PDF資料 |
PDF描述 |
|---|---|
| W3H32M72E-SBI | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-SBM | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-XSBX | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-400ES | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-400ESC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H32M72E-SBI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-SBM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-XSBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M16E-400BI | 制造商:Microsemi Corporation 功能描述:64M X 64 DDR2, 1.8V, 400MHZ - Bulk |
| W3H64M64E-400SBC | 制造商:Microsemi Corporation 功能描述:64M X 64 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
發布緊急采購，3分鐘左右您將得到回復。