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參數資料
| 型號： | W3H32M72E-SBC |
| 英文描述： | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 32M × 72配置DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 4/30頁 |
| 文件大小： | 934K |
| 代理商： | W3H32M72E-SBC |
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W3H32M72E-XSBX
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
February 2006
Rev. 2
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
TABLE 1 – BALL DESCRIPTIONS
Symbol
Type
Description
ODT
Input
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and
UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing
of the positive edge of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the
crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the
DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration
and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks
idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down
exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding
CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.
CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V
CC
is applied during first power-up. After
V
REF
has become stable during the power on and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF-REFRESH operation, V
REF
must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands
are masked when CS# is registered HIGH.
CK, CK#
Input
CKE
Input
CS#
Input
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
LDM, UDM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled
HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM
loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for
upper byte DQ8–DQ15, of each of U0-U4
Bank address inputs: BA0–BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is
being applied. BA0–BA1 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the
LOAD MODE command.
BA0–BA1
Input
Continued on next page
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| W3H32M72E-SBI | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-SBM | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-XSBX | 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-400ES | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H32M72E-SBI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-SBM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M72E-XSBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M16E-400BI | 制造商:Microsemi Corporation 功能描述:64M X 64 DDR2, 1.8V, 400MHZ - Bulk |
| W3H64M64E-400SBC | 制造商:Microsemi Corporation 功能描述:64M X 64 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
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