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參數(shù)資料
| 型號： | W3EG6433S-BD4 |
| 英文描述： | 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| 中文描述： | 256MB的- 32Mx64 DDR內(nèi)存緩沖，瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 334K |
| 代理商： | W3EG6433S-BD4 |
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-AD4
-BD4
May 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
(Continued)
AC CHARACTERISTICS
335
262
265/202
UNITS
NOTES
PARAMETER
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
SYMBOL
t
QH
t
QHS
t
RAS
t
RAP
t
RC
t
RFC
t
RCD
t
RP
t
RPRE
t
RPST
t
RRD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
NA
t
REFC
t
REFI
t
VTD
t
XSNR
t
XSRD
MIN
t
HP -
t
QHS
MAX
MIN
t
HP -
t
QHS
MAX
MIN
t
HP -
t
QHS
MAX
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
ns
t
CK
ns
μs
μs
ns
ns
t
CK
22, 23
0.55
70,000
0.75
120,000
0.75
120,000
42
15
60
72
15
15
0.9
0.4
12
0.25
0
0.4
15
1
40
15
60
75
15
15
0.9
0.4
15
0.25
0
0.4
15
1
40
20
65
75
20
20
0.9
0.4
15
0.25
0
0.4
15
1
31, 48
43
1.1
0.6
1.1
0.6
1.1
0.6
38
38
18, 19
17
0.6
0.6
0.6
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
22
21
21
70.3
7.8
70.3
7.8
70.3
7.8
0
0
0
75
200
75
200
75
200
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