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參數資料
| 型號： | W3EG6433S-BD4 |
| 英文描述： | 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| 中文描述： | 256MB的- 32Mx64 DDR內存緩沖，瓦特/鎖相環 |
| 文件頁數： | 5/13頁 |
| 文件大小： | 334K |
| 代理商： | W3EG6433S-BD4 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-AD4
-BD4
May 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ T
A
≤ 70°C, V
CCQ
= 2.5V ±0.2V, V
CC
= 2.5V ±0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5
Max
1275
DDR200@CL=2
Max
1235
Parameter
Symbol Conditions
One device bank; Active - Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge;
Burst = 2; t
RC
=t
RC
(MIN);t
CK
=t
CK
(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
All device banks idle; Power- down mode;
t
CK
=t
CK
(MIN); CKE=(low)
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
One device bank active; Power-down mode;
t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
RC
=t
RAS
(MAX);
t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst; One
device bank active;Address and control inputs
changing once per clock cycle; t
CK
=t
CK
(MIN);
Iout = 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control inputs
changing once per clock cycle; t
CK
=t
CK
(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
I
DD5
t
RC
=t
RC
(MIN)
I
DD6
CKE
≤
0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN);
Address and control inputs change only
during Active Read or Write commands.
Max
1276
Units
mA
Operating Current
I
DD0
Operating Current
I
DD1
1635
1555
1435
mA
Precharge Power-Down
Standby Current
I
DD2P
32
32
32
mA
Idle Standby Current
I
DD2F
675
635
635
mA
Active Power-Down
Standby Current
I
DD3P
240
200
240
mA
Active Standby Current
I
DD3N
755
675
675
mA
Operating Current
I
DD4R
1675
1475
1475
mA
Operating Current
I
DD4W
1675
1475
1475
mA
Auto Refresh Current
Self Refresh Current
2315
307
3555
2155
307
3075
2235
307
3195
mA
mA
mA
Operating Current
I
DD7A
* For DDR333 consult factory
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