- 您現在的位置：買賣IC網 > PDF目錄363884 > W3EG6433S-BD4 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL PDF資料下載
參數資料
| 型號： | W3EG6433S-BD4 |
| 英文描述： | 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| 中文描述： | 256MB的- 32Mx64 DDR內存緩沖，瓦特/鎖相環 |
| 文件頁數： | 7/13頁 |
| 文件大小： | 334K |
| 代理商： | W3EG6433S-BD4 |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-AD4
-BD4
May 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
UNITS
NOTES
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
SYMBOL
t
AC
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IHF
t
ISF
t
IHS
t
ISS
t
IPW
t
MRD
MIN
-0.70
0.45
0.45
6
7.5
0.45
0.45
1.75
-0.60
0.35
0.35
MAX
+0.70
0.55
0.55
13
13
MIN
-0.75
0.45
0.45
7.5
7.5
0.5
0.5
1.75
-0.75
0.35
0.35
MAX
+0.75
0.55
0.55
13
13
MIN
-0.75
0.45
0.45
7.5
7.5/10
0.5
0.5
1.75
-0.75
0.35
0.35
MAX
+0.75
0.55
0.55
13
13
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
26
26
CL = 2.5
CL = 2
40, 45
40, 45
23, 27
23, 27
27
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
+0.60
+0.75
+0.75
0.4
1.25
0.5
1.25
0.5
1.25
22, 23
0.75
0.20
0.20
t
CH,
t
CL
0.75
0.20
0.20
t
CH,
t
CL
0.75
0.20
0.20
t
CH,
t
CL
8
+0.70
+0.75
+0.75
16, 37
16, 37
12
12
12
12
-0.70
0.75
0.75
0.8
0.8
2.2
12
-0.75
0.90
0.90
1
1
2.2
15
-0.75
0.90
.900
1
1
2.2
15
相關PDF資料 |
PDF描述 |
|---|---|
| W3EG72126MS133JD3MG | 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126MS133JD3SF | 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126MS133JD3SG | 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126MS166AJD3MF | 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126MS166AJD3MG | 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3EG6433S-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
發布緊急采購，3分鐘左右您將得到回復。