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參數(shù)資料
| 型號(hào)： | W28V400B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY |
| 中文描述： | 4分（為512k × 8/256K × 16）SMARTVOLTA通用閃存 |
| 文件頁(yè)數(shù)： | 17/48頁(yè) |
| 文件大小： | 1822K |
| 代理商： | W28V400B |
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W28V400B/T
Publication Release Date: April 11, 2003
- 17 -
Revision A4
Table 6. Write Protection Alternatives
OPERATION
V
PP
V
IL
#RESET
#WP
EFFECT
X
X
All Blocks Locked.
V
IL
V
HH
X
All Blocks Locked.
X
All Blocks Unlocked.
V
IL
V
IH
2 Boot Blocks Locked.
Block Erase
or
Word/Byte Write
>
V
PPLK
V
HH
All Blocks Unlocked.
Table 7. Status Register Definition
WSMS
ESS
ES
WBWS
VPPS
WBWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = WORD/BYTE WRITE STATUS (WBWSLBS)
1 = Error in Word/Byte Write
0 = Successful Word/Byte Write
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
Check RY/#BY or SR.7 to determine block erase or
word/byte write completion. SR.6-0 are invalid while SR.7 =
"0".
If both SR.5 and SR.4 are "1"s after a block erase attempt,
an improper command sequence was entered.
SR.3 does not provide a continuous indication of V
PP
level.
The WSM interrogates and indicates the V
PP
level only after
Block Erase or Word/Byte Write command sequences. SR.3
is not guaranteed to reports accurate feedback only when
V
PP
≠
V
PPH1/2/3
.
The WSM interrogates the #WP and #RESET only after
Block Erase or Word/Byte Write command sequences. It
informs the system, depending on the attempted operation, if
the #WP is not V
IH
, #RESET is not V
HH
.
SR.0 is reserved for future use and should be masked out
when polling the status register.
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