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參數(shù)資料
| 型號： | WEDPNF8M721V-1012BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1012BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
mand sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the
two-cycle unlock bypass reset command sequence. The
first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are “don't care” for both cycles. The
device then returns to reading array data.
Figure 6 illustrates the algorithm for the program operation.
See the Erase/Program Operations table in the “Flash AC
Characteristics” for parameters, and to Figure 12 for timing
diagrams.
A
UTOSELECT
C
OMMAND
S
EQUENCE
The autoselect command sequence allows the host system
to determine whether or not a sector is protected. Table 7
shows the address and data requirements. This method is
an alternative to that shown in Table 6, which is intended for
PROM programmers and requires V
ID
on address bit FA9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command.
The device then enters the autoselect mode, and the sys-
tem may read at any address any number of times, without
initiating another command sequence.
A read cycle containing a sector address (SA) and the ad-
dress 02h in word mode (or 04h in byte mode) returns
02h in that sector is protected, or 00h if it is unprotected.
Refer to Table 5 for valid sector addresses.
The system must write the reset command to exit autoselect
mode and return to reading array data.
W
ORD
/B
YTE
P
ROGRAM
C
OMMAND
S
EQUENCE
The system may program the device by word or byte, de-
pending on the state of the BYTE1 pin. Programming is a
four-bus-cycle operation. The program command se-
quence is initiated by writing two unlock write cycles, fol-
lowed by the program set-up command. The program ad-
dress and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required
to provide further controls or timing. The device automati-
cally provides internally generated program pulses and veri-
fies the programmed cell margin. Table 7 shows the ad-
dress and data requirements for the byte program com-
mand sequence.
When the Embedded program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using FD7, FD6, or RY/BY1. See
“Write Operation Status” for information on these status bits.
F
IG
. 6 P
ROGRAM
O
PERATION
NOTE: See Table 7 for program command sequence.
相關(guān)PDF資料 |
PDF描述 |
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| WEDPNF8M721V-1012BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1012BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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