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參數資料
| 型號： | WCMA2008U1B-FF70 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K x 8 Static RAM |
| 中文描述： | 256K × 8靜態RAM |
| 文件頁數： | 5/11頁 |
| 文件大小： | 144K |
| 代理商： | WCMA2008U1B-FF70 |
WCMA2008U1B
5
Switching Characteristics
Over the Operating Range
[5]
Parameter
Description
WCMA2008U1B-70
Min.
Unit
Max.
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8,]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
5.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading
of the specified I
/I
and 30 pF load capacitance.
6.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
7.
t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
8.
The internal write time of the memory is defined by the overlap of WE, CE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE
1
LOW and CE
2
HIGH to Low Z
[6]
CE
1
HIGH or CE
2
LOW to High Z
[6, 7]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH or CE
2
LOW to Power-Down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
0
70
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10
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相關代理商/技術參數 |
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|---|---|
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