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參數(shù)資料
| 型號(hào)： | W9864AASA |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MB (8M x 64) SDRAM SO-DIMM MODULE(64MB (8M x 64)小型雙列直插同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 64MB的（8米× 64）SDRAM內(nèi)存的SO - DIMM模組（64兆（8米× 64）小型雙列直插同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 166K |
| 代理商： | W9864AASA |
W9864AASA
64MB (8M x 64) SDRAM SO-DIMM MODULE
Revision 0.9
11 OF
12
Publication Release Date:98/05/18
CONTENTS OF EEPROM (SPD Version 1.2)
FUNCTION SUPPORTED
HEX VALUE
BYTE NUMBER
FUNCTION DESCRIBED
-10/10L
-10/10L
0
Defines # bytes written into serial memory at module
manufacturer
Total # bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM..)
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Rows on this assembly
Data Width of this assembly…
Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycle time @CAS latency of 3
SDRAM Access time form clock @CAS latency of 3
DIMM Configuration type (Non-parity, Parity ECC)
Refresh Rate/Type
SDRAM width, Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay, Back Random Column
Addresses
Burst Lengths supported
#Bank on Each SDRAM device
CAS# Latencies Supported
CS# Latency
Write Latency
128 bytes
80h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
256 bytes (2K-bit)
SDRAM
12
8
2 row
64 bits
-
LVTTL
10ns
8ns
Non parity
15.625 us, support self refresh
X16
None
08h
04h
0Ch
08h
02h
40h
00h
01h
A0h
80h
00h
80h
10h
00h
15
TCCD=1 CLK
01h
16
17
18
19
20
1, 2, 4, 8 & full page
4 banks
2 & 3
0 CLK
0 CLK
Non-buffered Non –registered &
redundant addressing
+/-10% voltage tolerance, Burst
Read, Single bit Write,
precharge all, auto precharge
15ns
9ns
-
-
30ns
20ns
30ns
60ns
2 row of 32MB
3ns
1ns
3ns
1ns
-
Current release Intel spd 1.2
-
8Fh
04h
06h
01h
01h
21
SDRAM Module Attributes
00h
22
SDRAM Device Attributes: General
0Eh
23
24
25
26
27
28
29
30
31
32
33
34
35
SDRAM cycle time @CAS latency of 2
SDRAM access time form clock @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock @CAS latency of 1
Precharge to active command period (t
RP
)
Active to Active command period (t
RRD
)
Active to Read/Write command delay time(t
RCD
)
Minimum Active to precharge period (t
RAS
)
Density of each Row on Module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
Superset Information(may be used in future)
SPD Revision
Checksum for Bytes 0-62
Manufacturers code
Manufacturing location
Manufacturer’s Part Number
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel specification for frequency
CAS latency for 66MHz
Unused storage locations
F0h
90h
00h
00h
1Eh
14h
1Eh
3Ch
08h
30h
10h
30h
10h
00h
12h
E3h
36-61
62
63
64-71
72
73-90
91-92
93-94
95-98
99-125
126
127
128+
MFG Dep
MFG Dep
MFG Dep
MFG Dep
MFG Dep
MFG Dep
MFG Dep
66h
06h
FFh
66MHz
CAS latency of both 2 & 3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9864G2DH6 | 制造商:WINBOND 功能描述:New |
| W9864G2GH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K X 4 BANKS X 32BITS SDRAM |
| W9864G2GH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K X 4 BANKS X 32BITS SDRAM |
| W9864G2GH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K X 4 BANKS X 32BITS SDRAM |
| W9864G2GH-6C | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K X 4 BANKS X 32BITS SDRAM |
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