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參數資料
| 型號： | W9864AASA |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MB (8M x 64) SDRAM SO-DIMM MODULE(64MB (8M x 64)小型雙列直插同步動態RAM模塊) |
| 中文描述： | 64MB的（8米× 64）SDRAM內存的SO - DIMM模組（64兆（8米× 64）小型雙列直插同步動態內存模塊） |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 166K |
| 代理商： | W9864AASA |
W9864AASA
64MB (8M x 64) SDRAM SO-DIMM MODULE
Revision 0.9
10 OF
12
Publication Release Date:98/05/18
Serial Presence Detect EEPROM
The Serial Presence Detect (SPD) function is implemented using a 2,408-bit EEPROM component. This nonvolatile
storage device contains data for identifying the module type and various SDRAM organization and timing parameters. System
read operations to the EEPROM device occur using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0)
which provide the EEPROM Device Address.
SPD EEPROM DC OPERATING CONDITIONS
(Vcc=3.3V
±
0.3V)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
OUTPUT LOW VOTAGE, lout=3 mA
INPUT LEAKGE CURRENT, Vin=GND to V
cc
OUTPUT LEAKAGE CURRENT, V
OUT
=GND to V
cc
STANDBY CURRENT
SCL=SDA Vcc -0.3V, All other inputs=GND or 3.3V +10%
POWER SUPPLY CURRENT
SCL clock frequency =100KHz
SYMBOL
V
CC
V
IH
V
IL
V
OL
I
LI
I
LO
MIN
3.0
V
CC
×.7
-0.3
MAX
3.6
V
CC
+ .5
V
CC
×.3
0.4
1
1
UNIT
V
V
V
V
uA
uA
NOTES
I
OL
=3mA
I
SB
10
uA
I
CC
1
mA
SPD AC OPERATING CONDITIONS
(Vcc=3.3V
±
0.3V)
AC CHRARCTERICS
PARAMETER
SYMBOL
f
SCL
t
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
MIN
MAX
100
100
3.5
UNIT
KHz
ns
us
us
us
us
us
us
us
ns
us
ns
us
ns
ms
NOTES
SCL clock frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the bus must be free before a new transition can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
Data in Hold Time
Data in Setup Time
SDA and SCL Rise time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Note:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain
high the bus level pull-up resistor, and the device does not respond to its slave address.
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
15
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