
Preliminary W77E58
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PROGRAMMABLE CLOCK-OUT
Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can
be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software
must initiate it by setting bit T2OE = 1, C/T2 = 0 and CP/RL = 0. Setting bit TR2 will start the timer.
This mode is similar to the baud rate generator mode, it will not generate an interrupt while Timer 2
overflow. So it is possible to use Timer 2 as a baud rate generator and a clock generator at the same
time. The clock-out frequency is determined by the following equation:
The Clock-Out Frequency = Oscillator Frequency / [4 X (RCAP2H,RCAP2L) ]
T2CON.6
TR2 = T2CON.2
T2EX = P1.1
EXEN2 = T2CON.3
EXF2
T2=P1.0
Timer 2
Interrupt
TH2
TL2
RCAP2H
RCAP2L
Clock Source
Mode input
div. by 4 osc/2
div. by 64 osc/32
div. by 1024 osc/512
1/2
Figure 18. Programmable Clock-Out Mode
WATCHDOG TIMER
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be
caused if it is enabled. The interrupt will occur if the individual interrupt enable and the global enable
are set. The interrupt and reset functions are independent of each other and may be used separately
or together depending on the users software.