
W741C240
Publication Release Date: May 1999
- 11 -
Revision A1
Interrupts
The W741C240 provides two internal interrupt sources (Divider 0, Timer 1) and one external interrupt
sources (port RC). Vector addresses for each of the interrupts are located in the range of program
memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the
interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been
set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited
until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by
executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be
released momentarily and the interrupt subroutine will be executed. After the RTN instruction is
executed in an interrupt subroutine, the
μ
C will enter hold mode again. The operation flow chart is
shown in Figure 7. The control diagram is shown below.
S
R
Q
S
R
Q
S
R
Q
IEF.0
IEF.2
Interrupt
Process
Circuit
Interrupt
Vector
Generator
004H
00CH
020H
IEF.7
Initial Reset
CLR EVF,#I instruction
DIS INT instruction
Initial Reset
EN INT
MOV IEF,#I
Enable
EVF.2
EVF.0
EVF.7
Disable
Divider 0
overflow signal
Port RC
signal change
Timer 1
underflow signal
Figure 6. Interrupt Event Control Diagram
Stop Mode Operation
In stop mode, all operations of the
μ
C cease (including the operation of the oscillator). The
μ
C enters
stop mode when the STOP instruction is executed and exits stop mode when an external trigger is
activated (by a falling signal on the RC port). When the designated signal is accepted, the
μ
C
awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It
will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the
NOP instruction should follow the STOP command.