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參數資料
| 型號： | W6693A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | USB Bus ISDN S/T Interface Controller(USB總線的ISDN S/T接口控制器) |
| 中文描述： | USB總線綜合業務數字網的S / T接口控制器（綜合業務數字網的USB總線的S / T的接口控制器） |
| 文件頁數： | 21/32頁 |
| 文件大小： | 423K |
| 代理商： | W6693A |
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Preliminary Data Sheet
W6694 Passive USB-ISDN S/T-Controller
-21-
Publication Release Date: March., 2000
Revision 0.93
8.2 Chip and FIFO Control Registers
8.2.1 Interrupt Mask Register
Value after reset: E1h
7
6
ICC
MOC
Setting ‘1’ to each bits masks the corresponding interrupt sources in ISTA register.
IMASK
Read/Write Address 00h
5
4
0
3
0
2
0
1
0
0
PIOIC
WAKE
8.2.2 Command Register 1
Value after reset: 00h
Writing 1 to the following bits will activate each corresponding function. Writing 0 to these bits has no effect.
7
6
5
4
3
DXRST
DRRST
DXEN
DREN
SRST
DXRST D Channel Transmitter Reset
Setting this bit resets D channel transmitter, and clear transmit FIFO (XFIFO). The transmitter will immediately
transmit inter frame time fill pattern (all 1’s) to D channel in ISDN layer 1, but the XFIFO is disabled (not active).
Software must issue DXEN to enable (activate) D channel XFIFO. After reset is done, this bit becomes 0. If this bit
and other bits are set at the same time, the reset action will be performed first and completed, then other actions will
follow.
DRRST D Channel Receiver Reset
Setting this bit resets D channels receiver, and clear receive FIFO (RFIFO). The D channels is disabled (not active).
Software must issue DREN to enable (activate) D channel RFIFO, in order to receive D channel data from ISDN,
and send data to USB. After reset is done, this bit becomes 0. If this bit and other bits are set at the same time, the
reset action will be performed first and completed, then other actions will follow.
DXEN D Channel Transmit FIFO Enable
Setting this bit enables D channel transmit FIFO (XFIFO). After enabled, the D channel XFIFO will begin to
receive D channel data from USB, and send data to ISDN. After enabled, this bit becomes 0.
DREN D Channel Receive FIFO Enable
Setting this bit enables D channel receive FIFO (RFIFO). After enabled, the D channel RFIFO will begin to receive
D channel data from ISDN, and send data to USB. After enabled, this bit becomes 0.
SRST Software Reset
Setting this bit internally generates a software reset signal. The effect of this reset signal is equivalent to hardware
reset pin, except that the USB circuit and all USB configured data are not reset. After reset is done, this bit becomes
0. This bit must be set along, i.e., all other bits in this register must not set at the same time.
CISOE Clear Isochronous-OUT Error
CMDR1
Write
Address 01h
2
1
0
CISOE
DLP
RLP
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W66ARX-18 | 制造商:Magnecraft 功能描述: |
| W66MAF185X | 制造商:Panasonic Industrial Company 功能描述:CRT |
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