
Preliminary Data Sheet
W6694 Passive USB-ISDN S/T-Controller
-17-
Publication Release Date: March., 2000
Revision 0.93
7.1.7 Isochronous-IN Transaction (Endpoint 5)
After power on or reset, all B and D channels receive FIFO (RFIFO) are disabled. A disabled RFIFO can not receive
data from ISDN, and will always return zero-length data for Isochronous-IN transaction. RFIFO can only be enabled by
command CMDR:REN. Once enabled, an Isochronous-IN transaction can read data from RFIFO of that channel. The data
packet also carries XFIFO status for that channel, and the most recent Isochronous-OUT packet error status (if error ever
occurred).
The packet format of Isochronous-IN is as below:
Bit 7
6
5
4
3
ISOE
D_XFR
D_XCOL
D_XDOV
D_XDUN
D_RDOV
D_DATA
...
B1_XFR
B1_XDOV
B1_XDUN B1_RDOV
B1_LEN3
B1_DATA
...
B2_XFR
B2_XDOV
B2_XDUN B2_RDOV
B2_LEN3
B2_DATA
...
ISOE
Isochronous-OUT Error
This bit is set to indicate that the most recent received Isochronous-OUT packet has CRC error. This bit will remain
set, until a CMDR1:CISOE clears it.
XCOL Transmit Collision (D channel only)
This bit indicates a D channel collision on the S-bus has been detected. The data in D channel XFIFO will be
automatically re-transmitted, until the whole HDLC frame are successfully transmitted. This bit will remain set,
until software issue CMDR1:DXEN to clear this bit.
XFR
Transmit FIFO Ready
It is set when XFIFO has at least half of the XFIFO size available for incoming USB data.
XDUN Transmit Data Under-run
The corresponding XFIFO has run out of data. For D and B channel, the XFIFO is reset and disabled for that
channel. This bit is cleared when XFIFO is enabled by XEN bit.
XDOV Transmit Data Overflow
The corresponding XFIFO has overflow condition. Data in XFIFO are overwritten by incoming USB data. For D
and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is enabled by XEN
bit.
RDOV Receive Data Overflow
The corresponding RFIFO has overflow condition. Data in RFIFO are overwritten by incoming ISDN data. When
overflow condition occurred, the D and B channel RFIFO is reset and disabled for that channel. This bit is cleared
when RFIFO is enabled by REN bit.
2
D_LEN2
1
D_LEN1
0
D_LEN0
B1_LEN2
B1_LEN1
B1_LEN0
B2_LEN2
B2_LEN1
B2_LEN0