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參數資料
| 型號： | W6692 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 30/84頁 |
| 文件大小： | 473K |
| 代理商： | W6692 |
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W6692
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7.6.1 D Channel Message Transfer Modes
The D channel HDLC controller operates in transparent mode.
Chracteristics:
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Receive frame address recognition
Address comparison maskable bit-by-bit
Flag generation / deletion
Zero bit insertion/ deletion
Frame Check Sequence (FCS) generation/ check with CRC_ITU-T
Note. The LAPD protocol uses the CRC_ITU-T for Frame Check Sequence. The polynominal is X
16
+ X
12
+ X
5
+ 1.
For address recognition, the W6692 provides four programmable registers for individual SAPI and
TEI values, SAP1-2 and TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. The
SAPG equals FEH or FCH which corresponds to SAPI = 63 for layer management procedure. The
TEIG equals FFH which corresponds to TEI = 127 for automatic TEI assignment procedure. The
address combinations are:
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SAP1 + TEI1
SAP1 + FFH
SAP2 + TEI2
SAP2 + FFH
FEH (FCH) + TEI1
FEH (FCH) + TEI2
FEH (FCH) + FFH
The receive frame address comparisons can be disabled (masked) per bit basis with the D_SAM and
D_TAM registers, but comparisons with the SAPG or TEIG cannot be disabled.
7.6.2 Reception of Frames in D Channel
A 128-byte FIFO is provided in the receive direction. The data movement between receive FIFO and
micro-processor is handled by interrupts.
There are two interrupt sources: Receive Message Ready (D_RMR) and Receive Message End
(D_RME). The D_RMR interrupt indicates that at least 64 bytes of data have been received and the
message/ frame is not ended. Upon D_RMR interrupt, the micro-processor reads out 64 bytes of data
from the FIFO. The D_RME interrupt indicates the last segment of a message or a message with
length
≤
64 bytes has been received. The length of data is less than or equal to 64 and is specified in
the D_RBCL register.
If the length of the last segment of message is 64, only D_RME interrupt is generated and the RBC5-
0 bits in D_RBCL register are 000000B.
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PDF描述 |
|---|---|
| W6693A | USB Bus ISDN S/T Interface Controller(USB總線的ISDN S/T接口控制器) |
| W6694 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| W6810 | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IE | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IR | SINGLE-CHANNEL VOICEBAND CODEC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
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