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參數資料
| 型號： | W66910CD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | TE Mode ISDN S/T-Controller with Microprocessor Interface |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, QFP-100 |
| 文件頁數： | 4/81頁 |
| 文件大小： | 681K |
| 代理商： | W66910CD |
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Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-4 -
8.1 C
HIP
C
ONTROL AND
D_
CH
HDLC
CONTROLLER
................................................................................................................. 42
8.1.1 D_ch receive FIFO
D_RFIFO Read Address 00H................................................................................................... 44
8.1.2 D_ch transmit FIFO
D_XFIFO Write Address 01H ................................................................................................ 44
8.1.3 D_ch command register
D_CMDR Write Address 02H............................................................................................ 45
8.1.4 D_ch Mode Register
D_MODE Read/Write Address 03H....................................................................................... 45
8.1.5 Timer 1 Register
TIMR1 Read/Write Address 04H................................................................................................... 46
8.1.6 Interrupt Status Register
ISTA Read_clear Address 05H........................................................................................... 47
8.1.7 Interrupt Mask Register
IMASK Read/Write Address 06H....................................................................................... 48
8.1.8 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 07H ..................................................................... 48
8.1.9 D_ch Extended Interrupt Mask Register
D_EXIM Read/Write Address 08H............................................................ 49
8.1.10 D_ch Transmit Status Register
D_XSTA Read Address 09H................................................................................... 49
8.1.11 D_ch Receive Status Register
D_RSTA Read Address 0AH .................................................................................... 50
8.1.12 D_ch SAPI Address Mask
D_SAM Read/Write Address 0BH............................................................................. 50
8.1.13 D_ch SAPI1 Register
D_SAP1 Read/Write Address 0CH...................................................................................... 50
8.1.14 D_ch SAPI2 Register
D_SAP2 Read/Write Address 0DH...................................................................................... 51
8.1.15 D_ch TEI Address Mask
D_TAM Read/Write Address 0EH.................................................................................. 51
8.1.16 D_ch TEI1 Register
D_TEI1 Read/Write Address 0FH .......................................................................................... 51
8.1.17 D_ch TEI2 Register
D_TEI2 Read/Write Address 10H........................................................................................... 51
8.1.18 D_ch Receive Frame Byte Count High
D_RBCH Read Address 11H...................................................................... 52
8.1.19 D_ch Receive Frame Byte Count Low
D_RBCL Read Address 12H........................................................................ 52
8.1.20 Timer 2
TIMR2 Write Address 13H....................................................................................................................... 52
8.1.21 Layer 1_Ready Code
L1_RC Read/Write Address 14H........................................................................................... 53
8.1.22 Control Register
CTL Read/Write Address 15H.................................................................................................... 53
8.1.23 Command/Indication Receive Register
CIR Read Address 58H/16H....................................................................... 54
8.1.24 Command/Indication Transmit Register
CIX Read/Write Address 17H................................................................... 54
8.1.25 S/Q Channel Receive Register
SQR Read Address 18H........................................................................................... 55
8.1.26 S/Q Channel Transmit Register
SQX Read/Write Address 19H................................................................................ 55
8.1.27 Peripheral Control Register
PCTL Read/Write Address 1AH.................................................................................. 56
8.1.28 Monitor Receive Channel 0
MO0R Read Address 1BH ........................................................................................... 57
8.1.29 Monitor Transmit Channel 0
MO0X Read/Write Address 1CH................................................................................ 57
8.1.30 Monitor Channel 0 Interrupt Register
MO0I Read_clear Address 1DH................................................................... 57
8.1.31 Monitor Channel 0 Control Register
MO0C Read/Write Address 1EH................................................................... 58
8.1.32 GCI Mode Control/Status Register
GCR Read/Write Address 1FH.......................................................................... 58
8.1.33 Peripheral Data Register 1
XDATA1 Read/Write Address 3DH .............................................................................. 59
8.1.34 Peripheral Data Register 2
XDATA2 Read/Write Address 3EH............................................................................... 60
8.1.35 Monitor Receive Channel 1 Register
MO1R Read Address 40H ............................................................................. 60
8.1.36 Monitor Transmit Channel 1 Register
MO1X Read/Write Address 41H.................................................................. 61
8.1.37 Monitor Channel 1 Interrupt Register
MO1I Read_clear Address 42H.................................................................... 61
8.1.38 Monitor Channel 1 Control Register
MO1C Read/Write Address 43H.................................................................... 61
8.1.39 GCI IC1 Receive Register
C1R Read Address 44H ................................................................................................ 62
8.1.40 GCI IC1 Transmit Register
C1X Read/Write Address 45H..................................................................................... 62
8.1.41 GCI IC2 Receive Register
C2R Read Address 46H ................................................................................................ 62
8.1.42 GCI IC2 Transmit Register
C2X Read/Write Address 47H..................................................................................... 62
8.1.43 GCI CI1 Indication Register
CI1R Read Address 48H............................................................................................. 63
8.1.44 GCI CI1 Command Register
CI1X Read/Write Address 49H................................................................................... 63
8.1.45 GCI Extended Interrupt Register
GCI_EXIR Read_clear Address 4AH................................................................. 63
8.1.46 GCI Extended Interrupt Mask Register
GCI_EXIM Read/Write Address 4BH ....................................................... 64
8.2 B1 HDLC
CONTROLER
...................................................................................................................................................... 64
8.2.1 B1_ch receive FIFO
B1_RFIFO Read Address 20H.................................................................................................. 65
8.2.2 B1_ch transmit FIFO
B1_XFIFO Write Address 21H............................................................................................... 65
8.2.3 B1_ch command register
B1_CMDR Read/Write Address 22H................................................................................. 66
8.2.4 B1_ch Mode Register
B1_MODE Read/Write Address 23H..................................................................................... 67
8.2.5 B1_ch Extended Interrupt Register
B1_EXIR Read_clear Address 24H .................................................................. 68
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PDF描述 |
|---|---|
| W6691 | ISDN S/T Interface Transceiver |
| W6691CD | ISDN S/T Interface Transceiver |
| W6691CP | ISDN S/T Interface Transceiver |
| W6692 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6691CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6691CP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6692 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCI Bus ISDN S/T-Controller |
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
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