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參數(shù)資料
| 型號(hào)： | W536A031 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 音頻合成 |
| 英文描述： | VOICE/MELODY/LCD CONTROLLER |
| 中文描述： | 30 SEC, SPEECH SYNTHESIZER |
| 封裝： | COB |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大小： | 643K |
| 代理商： | W536A031 |
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W536A031
- 6 -
4. PAD DESCRIPTION
SYMBOL
I/O
FUNCTION
XIN/RXIN
I
Input pad for main clock oscillator. It can be connected to crystal when
crystal mode is selected (SCR0.2 = 1), otherwise connect a resistor to
V
DD
to generate main system clock while Ring mode is selected
(SCR0.2 = 0 and default). Oscillator can be enabled or stopped by set
SCR0.1 to 1 or clear to 0 separately. External capacitor connects to
start oscillation while crystal mode and get more accurate clock when
crystal mode
XOUT
O
Output pad for oscillator, which is connected to another crystal pad
when in crystal mode. External capacitor connects to start oscillation
when in crystal mode.
X32I/RSUB1
I
32.768 KHz crystal input pad or external resistor node 1
by mask
option
. External 15~20pF capacitor connects to start oscillation and
get more accurate clock when in crystal mode.
X32O/RSUB2
O
32.768 KHz crystal output pad or external resistor node 2
by mask
option.
External 15~20pF capacitor connects to start oscillation and
get more accurate clock when in crystal mode.
RA0 ~ RA3/TONE
(7)
I/O
General Input/Output port specified by PM1 register. If output mode is
selected, PM0 register bit 0 can be used to specify CMOS/NMOS
driving capability option (7). Initial state is input mode. RA3 may be
uses as TONE if bit 0 of MR0 special register is set to logic 1. An
interrupt source.
RB0 ~ RB3
(7)
I/O
General Input/Output port specified by PM2 register. If output mode is
selected, PM0 register bit 1 can be used to specify CMOS/NMOS
driving capability option (7). Initial state is input mode
RC0 ~ RC3
I
4-bit schmitter input with internal pull high option specified by PM3
register bit 2. Each pad has an independent interrupt capability
specified by PEFL special register. Interrupt and STOP mode wake up
source. RC0 is also the external event counter source of Timer1.
RD0
RD1/ADDR
RD2/DATA
RD3/CLK
(4)
I
4-bit schmitter input port with internal pull high option specified by PM3
register bit 3. Each pad has an independent interrupt capability
specified by PEFH special register. Interrupt and STOP mode wake up
source. RD1~3 will be shared as the external memory W55XXX
interface pads while RD port shared as serial bus mask option is
enabled.
"Tri-state serial bus" mask option can use to float CLK/ADDR/SPDATD
while "RD port shared as serial bus" mask option is enabled.
RES
TEST
I
System reset pad, active low with internal pull-high resistor.
I
Test pad. Active high with internal pull low resistor.
ROSC
I
Connect resistor to V
DD
pad to generate speech or melody playing
clock source.
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