
W536A031
Publication Release Date: May 20, 2003
- 3 -
Revision A2
2. FEATURES
Operating voltage: 2.4 volt ~ 5.5 volt
Watch dog disabled/enabled by mask option
Dual clock operating system
Main clock with Ring/Crystal (400 KHz to 4 MHz)
Sub-clock with 32.768 KHz RC/Crystal by mask option
Memory
Program ROM (P-ROM): 32K
×
20 (ROM Bank0, 1, 2)
Data RAM (W-RAM): 1.4K
×
4 bit
(RAM Bank 0 is 896 nibbles from 0:000 ~0:37F and 0:380~0:3FF are mapped to special
register.
RAM Bank F is 512 nibbles from F: 200 ~F: 3FF either data RAM or dedicated to script kernel)
LCD RAM (L-RAM): 256
×
4 bit
×
2 pages (RAM Bank1, 2 from 200~2FF)
16 input/output pads
Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory
W55XXX interface @W536A031)
Ports for Input/output: 8 pads (RA and RB port; RB port is available)
Power-down mode
Hold mode (except for 32kHz oscillator)
Stop mode (including 32kHz oscillator and release by RD or RC port)
Eight types of interrupts
Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Meloy)
Three external interrupts (Port RC, RD, RA)
One built-in 14-bit clock frequency divider circuit
Two built-in 8-bit programmable countdown timers
Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0
Built-in 18/14-bit watchdog timer for system reset.
Powerful instruction sets
8-level subroutine (including interrupt) nesting
LCD driver unit capability
VLCD higher than (VDD-0.5V)
Built-in voltage regulator to V2 pad
64 seg
×
16 com
1/16 or 1/8 duty, 1/5 or 1/4 bias, internal pump circuit option by special register
COM 8~ 15 and SEG40~63 can be shared as general input/output by special register
Either uC ROM or voice ROM used as LCD picture