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參數資料
| 型號： | W53322 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 60" Voice/Melody/LCD Controller(60”話音/音樂/LCD控制器) |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 文件頁數： | 15/65頁 |
| 文件大小： | 719K |
| 代理商： | W53322 |
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W53322/W53342
Publication Release Date: March 1999
- 15 -
Revision A2
MOV TM0L(TM0H),R instructions. To execute MOV TM0L(TM0H),R instructions will stop TM0 down-counting if the TM0 is
processing down-counting, reset TM0EN option bit (bit 3 of MR0 special register) to 0, and load specified value to TM0.
When TM0EN is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. Timer 0 stops operating and
generates an underflow (EVF.1 = 1) while it decrements to FFH. The interrupt is executed if the Timer 0 interrupt enable
flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1).
The Timer 0 clock input can select either F
OSC
/1024 or F
OSC
/4 by setting TM1CK (bit 2 of MR1 special register) to 1 or
resetting TM1CK to 0. The organization of Timer 0 is shown in Figure 6.
Example:
If the Timer 0 clock input is F
OSC
/4, then:
Desired Time 0 interval = (preset value +1)
×
4
×
1/F
OSC
If the Timer 0 clock input is F
OSC
/1024, then:
Desired Time 0 interval = (preset value +1)
×
1024
×
1/F
OSC
Preset value: Decimal number of Timer 0 preset value
Fosc/4
Fosc/1024
Enable
(1)
Disable
(0)
1. Reset
2. CLR EVF,#02H
3. Reset TM0EN
4. MOV TM0L,R or MOV TM0H,R
8-Bit Binary
Down Counter
(Timer 0)
S
R
Q
HEF.1
IEF.1
Hold mode release (HCF.1)
Timer 0 interrupt (INT1)
1. Reset
2. CLR EVF,#02H
3.Set TM0EN
EVF.1
MR1.2
(TM0CK)
MR0.3
(TM0EN)
4
4
MOV TM0H,R
MOV TM0L,R
(0)
(1)
Figure 6. Organization of Timer 0
2. Timer 1 (TM1)
Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 7. Timer 1 can be used as a counter
to count external events or to output an arbitrary frequency to the RE3/TONE pin. The input clock source of Timer 1 can
be internal or sub-frequency/4 (32768/4) Hz clock by TM1SR option bit (bit 1 of MR1 special register). The internal clock
can be selected F
OSC
/64 or F
OSC
by TM1CK option bit (bit 0 of MR1 special register) At initial reset, the Timer 1 clock
input is F
OSC
. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at
the falling edge of RC.0. To execute MOV TM1L, R or MOV TM1H,R instruction will load specified data to the auto-reload
buffer and disable TM1 down-counting (i.e. TM1EN is reset to 0). If TM1EN is set 1 , the contents of the auto-reload
buffer will be loaded into the TM1 down counter to start counting and reset the event flag 7 (EVF.7 = 0). When the timer
decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it
will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the
hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1).
The specified frequency of Timer 1 can also be output to the RE3/TONE pin by TONE option bit(bit 0 of MR0).
Example:
If the Timer 1 clock input is F
T, then
:
Desired Timer 1 interval = (preset value +1) / F
T
Desired frequency for RE3/TONE output pin = F
T
÷
(preset value + 1)
÷
2 (Hz)
Preset value: Decimal number of Timer 1 preset value
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