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參數(shù)資料
| 型號(hào)： | W53322 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 60" Voice/Melody/LCD Controller(60”話音/音樂/LCD控制器) |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER |
| 文件頁數(shù)： | 11/65頁 |
| 文件大小： | 719K |
| 代理商： | W53322 |
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W53322/W53342
Publication Release Date: March 1999
- 11 -
Revision A2
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D~3F ------
MR2(r/w,s/c)
MR3(w)
MR0(r/w,s/c)
MR1(w)
LCDM1(w)
SCR(r/w,s/c)
LUP0(r/w)
LUP1(r/w)
LUP2(r/w)
LUP3(r/w)
WRPAGE(r/w)
LUC(r)
PM0(r/w,s/c)
-----
PSR0(r,clr-all)
PSR1(r,clr-all)
PM1(r/w,s/c)
PM2(r/w,s/c)
PORTA(r/w)
PORTB(r/w)
PORTC(r)
PORTD(r)
PORTE(w)
special register for interrupt enable
Mode register 3
Mode Register 0 for timer
Mode Register 1 for timer
LCD Mode register 1
System Control Register
Look UP table address pointer first nibble LUPC.3~LUPC.0
Look UP table address pointer 2nd nibble LUPC.7~LUPC.4
Look UP table address pointer 3th nibble LUPC.11~LUPC.8
Look UP table address pointer 4th nibble X,X,LUPC.13,LUPC.12
Working Register PAGE register
LUPC nibble counter
Port Mode Register 0
X,X,X,INTEN
Vlcd, FsENB, PWM1, PWM0
TM0EN,TM1EN,LCDEN,TONE
WDTCK,TM0CK,TM1SR,TM1CK
COM32B,BIAS7B,PUPV3B,INTSRB
DIV5MB,FMRCB,FMEN,F32IN
0000~1101H
0000~0100H
RD_PH,RC_PH,RB_NM,RA_NM
Port RC Status change Register
Port RD Status chabge Register
Port RA I/O Mode select Register
Port RB I/O Mode select Register
PORT data of RA
PORT data of RB
PORT data of RC
PORT data of RD
PORT data of RE
RC3EG~RC0EG
RD3EG~RD0EG
RA3IN~RA0IN
RB3IN~RB0IN
RA3~RA0
RB3~RB0
RC3~RC0
RD3~RD0
RE3~RE0
Note 1: "r, w, s,c " means "read, write, set, and clear" separately)
Note 2: "clr-all " means all 4 bit will be clear simultaneously.
Note 3: X means don't care bit
Table 2: Special Register address mapping
Accumulator (ACC)
The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the data memory,
I/O ports, and special registers.
Arithmetic and Logic Unit (ALU)
This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:
Logic operations: ANL, XRL, ORL
Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3, JNB0, JNB1,
JNB2, JNB3, SKNB0, SKNB1, SKNB2, SKNB3
Shift operations: SHRC, RRC, SHLC, RLC,
Binary additions/subtractions: ADDC, ADD, ADDU, SUB, SUBB, DEC, INC
After any of the above instructions are executed, the status of the carry flag (CF) and zero signal (ZF) will be influenced.
The CF will be stored to internal register, read out by executing MOVA R, CF or MOV CF, R.
Carrie Flag Register (CF with SR=20H)
The CF register is only stored the CF signal state. Please refer to instruction sets to know CF signal status.
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