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參數(shù)資料
| 型號： | W48C54A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Frequency Synthesizers(頻率合成器) |
| 中文描述： | 頻率合成器（頻率合成器） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 146K |
| 代理商： | W48C54A |
W48C54A/55A
6
Recommended Board Layout: W48C54A/55A
For optimum performance in system applications, the power
supply decoupling scheme shown in
Figure 1
should be used.
All GND pins are connected to the ground plane.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-
μ
F decoupling capacitors should be
placed as close to the V
DD
pins as possible, otherwise the
increased trace inductance will negate its decoupling capabil-
ity. the 10-
μ
F decoupling capacitor shown should be a tanta-
lum type. For further EMI protection, the V
DD
connection can
be made via a ferrite bead, as shown.
Document #: 38-00803
Ordering Information
Ordering Code
W48C54A
W48C55A
Freq. Mask
Code
05, 08, 09, 59
61
Package
Name
G
G
Package Type
16-pin Plastic SOIC (150-mil)
20-pin Plastic SOIC (300-mil)
0.1
μ
F
VDD
GND
GND
VDD
GND
0.1
μ
F
10
μ
F
V
DD
Optional
Ferrite Bead
Figure 1. Recommended Circuit Configuration
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