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參數(shù)資料
| 型號(hào)： | W48C111 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Frequency Generator for Integrated Core Logic |
| 中文描述： | 頻率發(fā)生器集成的核心邏輯 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 115K |
| 代理商： | W48C111 |
W48C111-16
PRELIMINARY
6
Document #: 38-00844
REF Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
Description
Test Condition/Comments
Frequency generated by crystal oscillator
CPU = 66.6/100 MHz
Unit
MHz
Min.
Typ.
14.318
Max.
Frequency, Actual
t
R
t
F
t
D
t
JC
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Jitter, Cycle to Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
500
ps
f
ST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
40
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100 MHz
Min.
Typ.
Unit
Max.
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
f
D
m/n
Deviation from 48 MHz
(48.008
–
48)/48
+167
ppm
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
t
R
t
F
t
D
t
JC
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Jitter, Cycle to Cycle
Measured on rising edge at 1.5V. Maximum dif-
ference of cycle time between two adjacent cy-
cles.
500
ps
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ordering Information
Ordering Code
W48C111
Freq. Mask
Code
-16
Package
Name
H
Package Type
28-pin SSOP (209 mils)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W48C111-16 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Frequency Generator for Integrated Core Logic |
| W48C111-16H | 功能描述:IC CLOCK GEN FREQ MOD 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| W48C111-16HT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| W48C111-17 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Mobile Motherboard System Clock |
| W48C20 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Audio Subsystem Clock Generator |
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