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參數資料
| 型號： | W48C101-01 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum BX System Frequency Generator(寬頻譜BX系統頻率發生器) |
| 中文描述： | 擴頻顏Bx系統頻率發生器（寬頻譜顏Bx系統頻率發生器） |
| 文件頁數： | 5/8頁 |
| 文件大小： | 111K |
| 代理商： | W48C101-01 |
W48C101-01
PRELIMINARY
5
AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5%,V
DDQ2
= 2.5V
±
5%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
Crystal Oscillator
V
TH
C
LOAD
C
IN,X1
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance
C
OUT
Output Pin Capacitance
L
IN
Input Pin Inductance
Notes:
3.
X1 input threshold voltage (typical) is V
/2.
4.
The W48C101-01 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 14 pF; this includes typical stray capacitance of short PCB traces to crystal.
5.
X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
X1 Input Threshold Voltage
[3]
Load Capacitance, as seen by External Crystal
[4]
X1 Input Capacitance
[5]
1.65
V
14
28
pF
pF
Pin X2 unconnected
Except X1 and X2
5
6
pF
pF
7
nH
DC Electrical Characteristics:
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
CPU = 66.6 MHz
CPU = 100 MHz
Unit
ns
Min.
15
Typ.
Max.
15.5
Min.
10
Typ.
Max.
10.5
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
1
4
V/ns
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
200
200
ps
t
SK
f
ST
Output Skew
Measured on rising edge at 1.25V
175
175
ps
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
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相關代理商/技術參數 |
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|---|---|
| W48C101-01H | 制造商:Cypress Semiconductor 功能描述: 制造商:IC WORKS 功能描述: |
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