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參數(shù)資料
| 型號： | W48C101-01 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum BX System Frequency Generator(寬頻譜BX系統(tǒng)頻率發(fā)生器) |
| 中文描述： | 擴頻顏Bx系統(tǒng)頻率發(fā)生器（寬頻譜顏Bx系統(tǒng)頻率發(fā)生器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 111K |
| 代理商： | W48C101-01 |
W48C101-01
PRELIMINARY
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:3
40, 39, 36,
35
O
CPU Clock Outputs 0 through 3:
These four CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI1:7
8, 10, 11, 13,
14, 16, 17
O
PCI Bus Clock Outputs 1 through 7:
These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
7
O
Fixed PCI Clock Output:
Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
CPU_STOP#
30
I
CPU_STOP# Input:
When brought LOW, clock outputs CPU0:3 are stopped LOW
after completing a full clock cycle (2
–
3 CPU clock latency). When brought HIGH,
clock outputs CPU0:3 start beginning with a full clock cycle (2
–
3 CPU clock latency).
PCI_STOP#
31
I
PCI_STOP# Input:
The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle.
SPREAD#
28
I
SPREAD# Input:
When brought LOW this pin activates Spread Spectrum clocking.
APIC0:1
45, 44
O
I/O APIC Clock Outputs:
Provides 14.318-MHz fixed frequency. The output volt-
age swing is controlled by VDDQ2.
48MHz
22, 23
O
48-MHz Outputs:
Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.
REF0:2
1, 2, 47
O
Fixed 14.318-MHz Outputs 0 through 2:
Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
SEL100/66#
SEL1:0
25, 26, 27
I
Frequency Selection Input:
Selects power-up default CPU clock frequency as
shown in
Table 1
on page 1.
X1
4
I
Crystal Connection or External Reference Frequency Input:
Connect to either
a 14.318-MHz crystal or reference signal.
X2
5
I
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
PWR_DWN#
29
I
Power Down Control:
When this input is LOW, device goes into a low-power con-
dition. All outputs are held LOW while in power-down. CPU and PCI clock outputs
are stopped LOW after completing a full clock cycle (2
–
3 CPU clock cycle latency).
When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at
full operating frequency (3 ms maximum latency).
VDDQ3
9, 15, 19, 21,
33, 48
P
Power Connection:
Connect to 3.3V supply.
VDDQ2
37,41,46
P
Power Connection:
Power supply for CPU0:3 and APIC0:1 output buffers. Connect
to 2.5V supply.
GND
3, 6, 12, 18,
20, 24, 32,
34, 38, 43
G
Ground Connection:
Connect all ground pins to the common system ground
plane.
NC
42
-
No Connect:
Do not connect.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W48C101-01H | 制造商:Cypress Semiconductor 功能描述: 制造商:IC WORKS 功能描述: |
| W48C101-01HT | 制造商:Cypress Semiconductor 功能描述: 制造商:IC Works Inc 功能描述:100 MHz, PROC SPECIFIC CLOCK GENERATOR, 48 Pin Plastic SMT |
| W48C101-01HTR | 制造商:IC_WORKS 功能描述: |
| W48C111 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Frequency Generator for Integrated Core Logic |
| W48C111-16 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Frequency Generator for Integrated Core Logic |
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