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參數(shù)資料
| 型號(hào)： | W3EG7218S265BD4 |
| 英文描述： | 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| 中文描述： | 128MB的- 16Mx72 DDR SDRAM的緩沖瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 177K |
| 代理商： | W3EG7218S265BD4 |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
November 2004
Rev. 1
PRELIMINARY
W3EG7218S-AD4
-BD4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
262
265/202
UNITS
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
NOTES
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
SYMBOL
t
AC
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IHS
t
ISS
t
IPW
t
MRD
MIN
-0.75
0.45
0.45
7.5
7.5
0.5
0.5
1.75
-0.60
0.35
0.35
MAX
+0.75
0.55
0.55
13
13
MIN
-0.75
0.45
0.45
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
MAX
+0.75
0.55
0.55
13
13
26
26
CL = 2.5
CL = 2
40, 45
40, 45
23, 27
23, 27
27
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
+0.75
+0.75
0.5
1.25
0.6
1.25
22, 23
0.75
0.2
0.2
0.75
0.2
0.2
t
CH,
t
CL
t
CH,
t
CL
30
+0.75
+0.75
16, 37
16, 37
12
12
-0.75
0.90
0.90
2.2
15
-0.75
1.1
1.1
2.2
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG7218S-AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S-BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG72255MS100AJD3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG72255MS100AJD3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG72255MS100JD3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
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