- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363884 > W3EG264M72EFSU403D4 1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA PDF資料下載
參數(shù)資料
| 型號： | W3EG264M72EFSU403D4 |
| 英文描述： | 1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA |
| 中文描述： | 1GB的- 2x64Mx72 DDR SDRAM，可緩沖，F(xiàn)BGA封裝 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 209K |
| 代理商： | W3EG264M72EFSU403D4 |
W3EG264M72EFSUxxxD4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ T
A
≤ +70°C; V
CC
= V
CCQ
= +2.5V ±0.2V
AC CHARACTERISTICS
403
PARAMETER
SYMBOL
MIN
Access window of DQs from CK/CK#
t
AC
-0.65
CK high-level width
t
CH
0.45
CK low-level width
t
CL
0.45
Clock cycle time
CL = 3
t
CK (3)
5
CL = 2.5
t
CK (2.5)
CL = 2
t
CK (2)
DQ and DM input hold time relative to DQS
t
DH
0.40
DQ and DM input setup time relative to DQS
t
DS
0.40
DQ and DM input pulse width (for each input)
t
DIPW
1.75
Access window of DQS from CK/CK#
t
DQSCK
-0.55
DQS input high pulse width
t
DQSH
0.35
DQS input low pulse width
t
DQSL
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
t
DQSS
0.72
DQS falling edge to CK rising - setup time
t
DSS
0.20
DQS falling edge from CK rising - hold time
t
DSH
0.20
Half clock period
t
HP
t
CH,
t
CL
Data-out high-impedance window from CK/CK#
t
HZ
Data-out low-impedance window from CK/CK#
t
LZ
-0.65
Address and control input hold time (fast slew rate)
t
IHF
0.60
Address and control input setup time (fast slew rate)
t
ISF
0.60
Address and control input hold time (slow slew rate)
t
IHS
0.8
335
262
265
UNITS NOTES
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
MAX
+0.65
0.55
0.55
10
MIN
-0.70
0.45
0.45
MAX
+0.70
0.55
0.55
MIN
-0.75
0.45
0.45
MAX
+0.75
0.55
0.55
MIN
-0.75
0.45
0.45
MAX
0.75
0.55
0.55
26
26
39, 44
39, 44
39, 44
23, 27
23, 27
27
6
13
13
7.5
7.5
0.5
0.5
1.75
-0.75
0.35
0.35
13
13
7.5
13
13
7.5
0.45
0.45
1.75
-0.60
0.35
0.35
7.5/10
0.5
0.5
1.75
-0.75
0.35
0.35
+0.55
+0.60
+0.75
+0.75
t
DQSQ
0.4
0.4
0.5
0.5
22, 23
1.25
0.75
0.20
0.20
1.25
0.75
0.20
0.20
1.25
0.75
0.2
0.2
1.25
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
30
+0.65
+0.65
+0.70
+0.75
+0.75
16, 36
16, 36
12
12
12
-0.70
0.75
0.75
0.8
-0.75
0.90
0.90
1
-0.75
0.90
0.90
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG264M72EFSUXXXD4 | 1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA |
| W3EG64128S202AD4 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S202BD4 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S262AD4 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S262BD4 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG264M72EFSUXXXD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA |
| W3EG64128S202AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S202BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG64128S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。