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參數(shù)資料
| 型號： | W3EG128M72ETSU-D3 |
| 英文描述： | 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| 中文描述： | 1GB的- 128Mx72 DDR SDRAM的無緩沖ECC瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 277K |
| 代理商： | W3EG128M72ETSU-D3 |
W3EG128M72ETSU-D3
-JD3
-AJD3
ADVANCED
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2005
Rev. 0
33. The voltage levels used are derived from a mini-mum V
CC
level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
34. V
IH
overshoot: V
IH
(MAX) = V
CCQ
+ 1.5V for a pulse width < 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
35. V
CC
and V
CCQ
must track each other.
36. t
HZ
(MAX) will prevail over t
DQSCK
(MAX) + t
RPST
(MAX) condition. t
LZ
(MIN) will
prevail over t
DQSCK
(MIN) + t
RPRE
(MAX) condition.
37. t
RPST
end point and t
RPRE
begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (t
RPST
), or begins driving
(t
RPRE
).
38. During initialization, V
CCQ
, V
TT
, and V
REF
must be equal to or less than V
CC
+ 0.3V.
Alternatively, V
TT
may be 1.35V maximum during power up, even if V
CC
/V
CCQ
are 0V, provided a minimum of 42 0 of series resistance is used between the V
TT
supply and the input pin.
39. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not reflect this option.
40. Random addressing changing and 50 percent of data changing at every transfer.
41. Random addressing changing and 100 percent of data changing at every transfer.
42. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t
REF
later.
43. I
DD2N
specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
I
DD2Q
is similar to I
DD2F
except I
DD2Q
specifies the address and control inputs to
remain stable. Although I
DD2F
, I
DD2N
, and I
DD2Q
are similar, I
DD2F
is “worst case.”
44. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles (before READ commands).
45. Leakage number reflects the worst case leakage possible through the module pin,
not what each memory device contributes.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. The 403 speed grade will operate with t
RAS
(MIN) = 40 ns and t
RAS
(MAX) =
120,000ns at any slower frequency.
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