
W39V040B
Publication Release Date: April 14, 2005
- 9 -
Revision A3
8. TABLE OF OPERATING MODES
8.1 Operating Mode Selection - Programmer Mode
PINS
MODE
#OE
#WE
#RESET
ADDRESS
DQ.
Read
V
IL
V
IH
V
IH
AIN
Dout
Write
V
IH
V
IL
V
IH
AIN
Din
Standby
X
X
V
IL
X
High Z
V
IL
X
V
IH
X
High Z/DOUT
Write Inhibit
X
V
IH
V
IH
X
High Z/DOUT
Output Disable
V
IH
X
V
IH
X
High Z
8.2 Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "START Cycle" when it is selected. When it
is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "LPC Cycle Definition".
8.3 LPC Cycle Definition
FIELD
NO. OF
CLOCKS
DESCRIPTION
Start
1
"0000b" appears on LPC bus to indicate the initial
Cycle Type & Dir
1
"010Xb" indicates memory read cycle; while "011xb" indicates
memory write cycle. "X" mean don't have to care.
TAR
2
Turned Around Time
Addr.
8
Address Phase for Memory Cycle. LPC supports the 32 bits address
protocol. The addresses transfer most significant nibble first and
least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first ,
and Address[3:0] on LAD[3:0] last.)
Sync.
N
Synchronous to add wait state. "0000b" means Ready, "0101b"
means Short Wait, "0110b" means Long Wait, "1001b" for DMA only,
"1010b" means error, other values are reserved.
Data
2
Data Phase for Memory Cycle. The data transfer least significant
nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0]
first, then DQ[7:4] on LAD[3:0] last.)