
W39V040B
Publication Release Date: April 14, 2005
- 4 -
Revision A3
3. PIN CONFIGURATIONS
A
1
0
^
F
G
P
I
4
v
5
6
7
9
10
11
12
13
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
^
L
A
D
1
v
V
S
S
D
Q
6
^
R
S
V
v
#
R
E
S
E
T
V
D
D
R
/
#
C
^
C
L
K
v
A
9
^
F
G
P
I
3
v
32L PLCC
DQ0(LAD0)
A7(FGPI1)
A6(FGPI0)
A4(#TBL)
A3(ID3)
A2(ID2)
A1(ID1)
A0(ID0)
A5(#WP)
MODE
DQ7(RSV)
#WE(#LFRAM)
#OE(#INIT)
NC
A
8
^
F
G
P
I
2
v
D
Q
2
^
L
A
D
2
v
D
Q
3
^
L
A
D
3
v
D
Q
4
^
R
S
V
v
D
Q
5
^
R
S
V
v
V
SS
RY/#BY(RSV)
V
DD
NC
V
P
P
#WE(#LFRAM
DQ4(RSV)
DQ3(LAD3)
DQ7(RSV)
DQ5(RSV)
#OE(#INIT)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32L STSOP
A3(ID3)
R/#C(CLK)
NC
VSS
Vpp
A10MODE
A9(FGPI3)
A7(FGPI1)
A5(#WP)
A4(#TBL)
#RESET
A2(ID2)
A1(ID1)
DQ0(LAD0)
VSS
NC
NC
4. BLOCK DIAGRAM
Program-
mer
Interface
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
00000
20000
1FFFF
10000
0FFFF
#RESET
MODE
#INIT
A[10:0]
DQ[7:0]
#OE
#WE
R/#C
LPC
Interface
#LFRAM
LAD[3:0]
64K BYTES BLOCK 0
30000
2FFFF
#WP
64K BYTES BLOCK 1
64K BYTES BLOCK 2
64K BYTES BLOCK 5
64K BYTES BLOCK 6
64K BYTES BLOCK 7
RY/#BY
64K BYTES BLOCK 3
64K BYTES BLOCK 4
7FFFF
70000
5. PIN DESCRIPTION
INTERFACE
PGM
*
*
SYM.
LPC
*
*
*
*
*
*
*
PIN NAME
MODE
#RESET
#INIT
#TBL
#WP
CLK
FGPI[4:0]
Interface Mode Selection
Reset
Initialize
Top Boot Block Lock
Write Protect
CLK Input
General Purpose Inputs
Identification Inputs They
Are Internal Pull Down to
Vss
Address/Data Inputs
LPC Cycle Initial
Row/Column Select
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
Ready/ Busy
Power Supply
Ground
Accelerate Program Power
Supply
Reserved Pins
No Connection
ID[3:0]
*
LAD[3:0]
#LFRAM
R/#C
A[10:0]
DQ[7:0]
#OE
#WE
RY/#BY
V
DD
V
SS
*
*
*
*
*
*
*
*
*
*
*
*
V
PP
*
*
RSV
NC
*
*
*
*